參數(shù)資料
型號： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 78/88頁
文件大?。?/td> 2015K
代理商： OR3L225B
78
Lucent Technologies Inc.
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Package Thermal Characteristics
There are four thermal parameters that are in common
use:
Θ
JA,
ψ
JC,
Θ
JC, and
Θ
JB
. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.
The data base containing the thermal values for all of
Lucent Technologies’ IC packages is currently being
updated to conform to modern JEDEC standards.
Thus, Table 32 contains the currently available thermal
specifications for Lucent Technologies’ FPGA pack-
ages mounted on both JEDEC and non-JEDEC test
boards. The thermal values for the newer package
types correspond to those packages mounted on a
JEDEC four-layer board. The values for the older pack-
ages, however, correspond to those packages mounted
on a non-JEDEC, single-layer, sparse copper board
(see Note 2). It should also be noted that the values for
the older packages are considered conservative.
Θ
JA
This is the thermal resistance from junction to ambient
(a.k.a.
Θ
-
JA
, R-
Θ
, etc.). It
is defined by the following:
where T
J
is the junction temperature, T
A
is the ambient
air temperature, and Q is the chip power.
Experimentally,
Θ
JA
is determined when a special ther-
mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (T
J
) is deter-
mined by the forward drop on the diodes, and the ambi-
ent temperature (T
A
) is noted. Note that
Θ
JA
is
expressed in units of °C/watt.
ψ
JC
This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by the following:
where T
C
is the case temperature at top dead center,
T
J
is the junction temperature, and Q is the chip power.
During the
Θ
JA
measurements described above,
besides the other parameters measured, an additional
temperature reading, T
C
, is made with a thermocouple
attached at top-dead-center of the case.
ψ
JC
is also
expressed in units of °C/watt.
Θ
JC
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by the following:
The parameters in this equation have been defined
above. However, the measurements are performed with
the case of the part pressed against a water-cooled
heat sink so as to draw most of the heat generated by
the chip out the top of the package. It is this difference
in the measurement process that differentiates
Θ
JC
from
ψ
JC.
Θ
JC
is a true thermal resistance and is
expressed in units of °C/watt.
Θ
JB
This is the thermal resistance from junction to board
(a.k.a.
Θ
JL
). It is defined by the following:
where T
B
is the temperature of the board adjacent to a
lead measured with a thermocouple. The other param-
eters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board so as to draw most of the
heat out of the leads. Note that
Θ
JB
is expressed in
units of °C/watt, and that this parameter and the way it
is measured is still in JEDEC committee.
Θ
JA
J
T
T
A
–
Q
=
ψ
JC
J
T
T
C
–
Q
=
Θ
JC
J
T
T
C
–
Q
=
Θ
JB
J
T
T
B
–
Q
=
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