參數(shù)資料
型號： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 24/88頁
文件大?。?/td> 2015K
代理商： OR3L225B
24
Lucent Technologies Inc.
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Timing Characteristics
(continued)
Table 13. Microprocessor Interface (MPI) Timing Characteristics
(continued)
OR3LxxB Commercial: V
DD
= 3.0 V to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 3.0 V
to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, –40 °C
<
T
A
<
+85 °C.
1. For user system flexibility,
CS0
and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge
when
MPI_STRB
is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and
CS0
and
CS1 may go inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC i960) from the FPGA.
PowerPCand i960timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
Symbol
Parameter
–7
–8
Unit
Min
Max
Min
Max
i960Interface Timing
(T
J
= 85 °C, V
DD
= min, V
DD
2 = min) (continued)
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
URDWR_DEL
User Read/Write Delay (pad to URDWR_DEL)
User Logic Delay
5
USTART_DEL
User Start Delay (MPI_CLK falling to USTART)
6
USTARTCLR_DEL User Start Clear Delay (MPI_CLK to USTART)
UEND_DEL
User End Delay (USTART low to UEND low)
7
Synchronous User Timing
UEND_SET
User End Setup (UEND to MPI_CLK)
UEND_HLD
User End Hold (UEND to MPI_CLK)
RDS_SET
Data Setup for Read (D[7:0] to MPI_CLK)
9
RDS_HLD
Data Hold for Read (D[7:0] from MPI_CLK)
9
Asynchronous User Timing
RDA_DEL
User End to Read Data Delay (UEND to D[7:0])
10
RDA_HLD
Data Hold from User Start (low)
9
TUIRQ_PW
Interrupt Request Pulse Width
8
Read/Write Setup Time
3
Read/Write Hold Time
4
Chip Select Setup Time (CS0, CS1 to CLK)
1
Chip Select Hold Time (CS0, CS1 from CLK)
1
User Address Delay (CLK low to UA[3:0])
—
—
0.80
0.0
—
—
—
—
—
—
6.21
4.60
—
—
0.70
0.0
—
—
—
—
—
—
4.00
ns
ns
ns
ns
ns
ns
—
—
—
3.80
6.90
—
—
—
—
3.30
6.00
—
ns
ns
ns
0.0
1.40
—
—
—
—
—
—
0.0
1.20
—
—
—
—
—
—
ns
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
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