參數(shù)資料
型號： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 14/88頁
文件大?。?/td> 2015K
代理商： OR3L225B
14
Lucent Technologies Inc.
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Timing Characteristics
(continued)
Table 6. Sequential PFU Timing Characteristics
OR3LxxB Commercial: V
DD
= 3.0 V to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 3.0 V
to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, –40 °C
<
T
A
<
+85 °C.
* Four-input variables’ (K
Z
[3:0]) setup times are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
Note: The table shows worst-case delays. ORCAFoundry reports the delays for individual paths within a group of paths representing the
same timing parameter and may accurately report delays that are less than those listed.
Symbol
Parameter
-7
-8
Unit
Min
Max
Min
Max
Input Requirements
CLKL_MPW
CLKH_MPW
GSR_MPW
LSR_MPW
Clock Low Time
Clock High Time
Global S/R Pulse Width (GSRN)
Local S/R Pulse Width
Combinatorial Setup Times (T
J
= +85 °C,
V
DD
= min, V
DD
2 = min):
Four-input Variables to Clock (Kz[3:0] to CLK)*
Five-input Variables to Clock (F5[A:D] to CLK)
Data In to Clock (DIN[7:0] to CLK)
Carry-in to Clock, DIRECT to REGCOUT (CIN to CLK)
Clock Enable to Clock (CE to CLK)
Clock Enable to Clock (ASWE to CLK)
Local Set/Reset to Clock (SYNC) (LSR to CLK)
Data Select to Clock (SEL to CLK)
Two-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Two-level LUT to Clock (F5[A:D] to CLK w/feedbk)
Three-level LUT to Clock (Kz[3:0] to CLK w/feedbk)*
Three-level LUT to Clock (F5[A:D] to CLK w/feedbk)
Combinatorial Hold Times (T
J
= all, V
DD
= all):
Data In (DIN[7:0] from CLK)
Carry-in from Clock, DIRECT to REGCOUT (CIN from
CLK)
Clock Enable (CE from CLK)
Clock Enable from Clock (ASWE from CLK)
Local Set/Reset from Clock (sync) (LSR from CLK)
Data Select from Clock (SEL from CLK)
All Others
1.00
0.76
1.00
1.00
—
—
—
—
0.87
0.66
0.87
0.87
—
—
—
—
ns
ns
ns
ns
F4_SET
F5_SET
DIN_SET
CINDIR_SET
CE1_SET
CE2_SET
LSR_SET
SEL_SET
SWL2_SET
SWL2F5_SET
SWL3_SET
SWL3F5_SET
0.90
0.51
0.21
0.68
1.41
1.11
0.69
0.64
1.79
1.46
3.06
2.67
—
—
—
—
—
—
—
—
—
—
—
—
0.78
0.44
0.18
0.59
1.23
0.97
0.60
0.55
1.55
1.27
2.66
2.32
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIN_HLD
CINDIR_HLD
CE1_HLD
CE2_HLD
LSR_HLD
SEL_HLD
—
0.0
0.0
0.0
0.0
0.0
0.0
0.0
—
—
—
—
—
—
—
0.0
0.0
0.0
0.0
0.0
0.0
0.0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
Output Characteristics
LSR_DEL
GSR_DEL
REG_DEL
LTCH_DEL
LTCHD_DEL
Sequential Delays (T
J
= +85 °C,
V
DD
= min, V
DD
2 = min):
Local S/R (async) to PFU Out (LSR to Q[7:0], REG-
COUT)
Global S/R to PFU Out (GSRN to Q[7:0], REGCOUT)
Clock to PFU Out—Register (CLK to Q[7:0], REG-
COUT)
Clock to PFU Out—Latch (CLK to Q[7:0])
Transparent Latch (DIN[7:0] to Q[7:0])
—
—
—
—
—
2.82
2.21
1.22
1.30
1.43
—
—
—
—
—
2.46
1.92
1.06
1.13
1.25
ns
ns
ns
ns
ns
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