參數(shù)資料
型號(hào)： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列）
文件頁(yè)數(shù)： 13/88頁(yè)
文件大小： 2015K
代理商： OR3L225B
Lucent Technologies Inc.
13
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Timing Characteristics
(continued)
In addition to supply voltage, process variation, and
operating temperature, circuit and process improve-
ments of the ORCA Series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed
grades higher than that designated on a product brand.
Design practices need to consider best-case timing
parameters (e.g., delays = 0), as well as worst-case
timing.
The routing delays are a function of fan-out and the
capacitance associated with the configurable interface
points (CIPs) and metal interconnect in the path. The
number of logic elements that can be driven (fan-out)
by PFUs is unlimited, although the delay to reach a
valid logic level can exceed timing requirements. It is
difficult to make accurate routing delay estimates prior
to design compilation based on fan-out. This is
because the CAE software may delete redundant logic
inserted by the designer to reduce fan-out, and/or it
may also automatically reduce fan-out by net splitting.
The waveform test points are given in the Input/Output
Buffer Measurement Conditions section of this data
sheet. The timing parameters given in the electrical
characteristics tables in this data sheet follow industry
practices, and the values they reflect are described
below.
Propagation Delay
—The time between the specified
reference points. The delays provided are the worst
case of the tphh and tpll delays for noninverting func-
tions, tplh and tphl for inverting functions, and tphz and
tplz for 3-state enable.
Setup Time
—The interval immediately preceding the
transition of a clock or latch enable signal, during which
the data must be stable to ensure it is recognized as
the intended value.
Hold Time
—The interval immediately following the
transition of a clock or latch enable signal, during which
the data must be held stable to ensure it is recognized
as the intended value.
3-State Enable
—The time from when a 3-state control
signal becomes active and the output pad reaches the
high-impedance state.
PFU Timing
Table 5. Combinatorial PFU Timing Characteristics
OR3LxxB Commercial: V
DD
= 3.0 V to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 3.0 V
to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, –40 °C
<
T
A
<
+85 °C.
* Four-input variables’ (K
Z
[3:0]) path delays are valid for LUTs in both F4 (four-input LUT) and F5 (five-input LUT) modes.
Symbol
Parameter
-7
-8
Unit
Min
Max
Min
Max
F4_DEL
F5_DEL
SWL2_DEL
SWL2F5_DEL
SWL3_DEL
SWL3F5_DEL
CO_DEL
Combinatorial Delays (T
J
= +85 °C, V
DD
=
min, V
DD
2 = min)
:
Four-input Variables (Kz[3:0] to F[z])*
Five-input Variables (F5[A:D] to F[0, 2, 4, 6])
Two-level LUT Delay (Kz[3:0] to F w/feedbk)*
Two-level LUT Delay (F5[A:D] to F w/feedbk)
Three-level LUT Delay (Kz[3:0] to F w/feedbk)*
Three-level LUT Delay (F5[A:D] to F w/feedbk)
C
IN
to C
OUT
Delay (logic mode)
—
—
—
—
—
—
—
1.03
0.85
2.30
1.91
3.40
3.02
1.66
—
—
—
—
—
—
—
0.90
0.74
2.00
1.66
2.96
2.63
1.44
ns
ns
ns
ns
ns
ns
ns
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