參數(shù)資料
型號： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 23/88頁
文件大?。?/td> 2015K
代理商： OR3L225B
Lucent Technologies Inc.
23
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Timing Characteristics
(continued)
Special Function Blocks Timing
Table 13. Microprocessor Interface (MPI) Timing Characteristics
OR3LxxB Commercial: V
DD
= 3.0 V to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 3.0 V
to 3.6 V, V
DD
2 = 2.38 V to 2.63 V, –40 °C
<
T
A
<
+85 °C.
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge
when MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and
CS1 may go inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (PowerPC, i960) from the FPGA.
PowerPC and i960timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
Symbol
Parameter
–7
–8
Unit
Min
Max
Min
Max
PowerPC nterface Timing
(T
J
= 85 °C, V
DD
= min, V
DD
2 = min)
TA_DEL
BI_DEL
TA_DELZ
BI_DELZ
WD_SET
WD_HLD
A_SET
A_HLD
RW_SET
RW_HLD
CS_SET
CS_HLD
UA_DEL
URDWR_DEL
Transfer Acknowledge Delay (CLK to TA)
Burst Inhibit Delay (CLK to BIN)
Transfer Acknowledge Delay to High Impedance
2
Burst Inhibit Delay to High Impedance
2
Write Data Setup Time (data to TS)
Write Data Hold Time (data from CLK while MPI_ACK low)
Address Setup Time (addr to TS)
Address Hold Time (addr from CLK while MPI_ACK low)
Read/Write Setup Time (R/W to TS)
Read/Write Hold Time (R/W from CLK while MPI_ACK low)
Chip Select Setup Time (CS0, CS1 to TS)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (pad to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
—
—
—
—
0.0
0.0
0.0
0.0
0.0
0.0
0.46
0.0
—
—
9.50
9.40
—
—
—
—
—
—
—
—
—
—
2.20
4.60
—
—
—
—
0.0
0.0
0.0
0.0
0.0
0.0
0.40
0.0
—
—
8.30
8.20
—
—
—
—
—
—
—
—
—
—
1.90
4.00
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i960Interface Timing
(T
J
= 85 °C, V
DD
= min, V
DD
2 = min)
ADSN_SET
ADSN_HLD
RDYRCV_DEL
RDYRCV_DELZ
WD_SET
WD_HLD
A_SET
A_HLD
BE_SET
BE_HLD
Addr/Data Select to ALE (ADS, to ALE low)
Addr/Data Select to ALE (ADS, from ALE low)
Ready/Receive Delay (CLK to RDYRCV)
Ready/Receive Delay to High Impedance
2
Write Data Setup Time
3
Write Data Hold Time
4
Address Setup Time (addr to ALE low)
Address Hold Time (addr from ALE low)
Byte Enable Setup Time (BE0, BE1 to ALE low)
Byte Enable Hold Time (BE0, BE1 from ALE low)
—
0.0
—
—
—
—
—
0.80
—
0.80
—
—
9.50
—
—
—
0.12
—
0.12
—
—
0.0
—
—
—
—
—
0.70
—
0.70
—
—
8.30
—
—
—
0.10
—
0.10
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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相關代理商/技術參數(shù)
參數(shù)描述
OR3L225B7BC432-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BC432I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BM680-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BM680I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B8BC432-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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