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| 型號(hào)： | OR3L225B |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 36/88頁 |
| 文件大?。?/td> | 2015K |
| 代理商： | OR3L225B |
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36
Lucent Technologies Inc.
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Timing Characteristics
(continued)
Table 22. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply V
DD
)
Table 23. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply V
DD
2)
Note:
The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay, paths
with more than 66% routing delay will derate at a higher rate
than shown in the table. The approximate derating values vs.
temperature are 0.26% per °C for logic delay and 0.45% per °C
for routing delay. The approximate derating values vs. voltage
are 0.13% per mV for both logic and routing delays at 25 °C.
In addition to supply voltage, process variation, and
operating temperature, circuit and process improve-
ments of the ORCA Series FPGAs over time will result
in significant improvement of the actual performance
over those listed for a speed grade. Even though lower
speed grades may still be available, the distribution of
yield to timing parameters may be several speed
grades higher than that designated on a product brand.
Design practices need to consider best-case timing
parameters (e.g., delays = 0), as well as worst-case
timing.
The routing delays are a function of fan-out and the
capacitance associated with the CIPs and metal inter-
connect in the path. The number of logic elements that
can be driven (fan-out) by PFUs is unlimited, although
the delay to reach a valid logic level can exceed timing
requirements. It is difficult to make accurate routing
delay estimates prior to design compilation based on
fan-out. This is because the CAE software may delete
redundant logic inserted by the designer to reduce fan-
out, and/or it may also automatically reduce fan-out by
net splitting.
T
J
(°C)
Power Supply Voltage
3.0 V
0.82
0.91
0.98
1.00
1.23
1.34
3.3 V
0.72
0.80
0.85
0.99
1.07
1.15
3.6 V
0.66
0.72
0.77
0.90
0.94
1.01
–40
0
25
85
100
125
T
J
(°C)
Power Supply Voltage
2.3 V
0.86
0.94
0.99
1.00
1.23
1.33
2.5 V
0.71
0.79
0.84
0.99
1.05
1.13
2.6 V
0.67
0.73
0.77
0.92
0.96
1.03
–40
0
25
85
100
125
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| OR3L225B7BC432-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3L225B7BC432I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3L225B7BM680-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3L225B7BM680I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3L225B8BC432-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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