參數(shù)資料
型號(hào)： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述： 現(xiàn)場(chǎng)可編程門陣列（現(xiàn)場(chǎng)可編程門陣列）
文件頁數(shù)： 1/88頁
文件大?。?/td> 2015K
代理商： OR3L225B
Data Addendum
December 1999
ORCA
OR3LxxxB Series
Field-Programmable Gate Arrays
Introduction
This data addendum refers to the information found
in the ORCA
Series 3C and 3T Field-Programmable
Gate Arrays Data Sheet.
Features
I
High-performance, cost-effective, 0.25 μm 5-level
metal technology.
I
2.5 V internal supply voltage and 3.3 V I/O supply
voltage for speed and compatibility.
I
Up to 340,000 usable gates
in 0.25 μm.
I
Up to 612 user I/Os in 0.25 μm. (OR3LxxxB I/Os
are 5 V tolerant to allow interconnection to both
3.3 V and 5 V devices, selectable on a per-pin
basis, when using 3.3 V I/O supply.)
I
Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables (LUTs)
per PFU, organized in two nibbles for use in nibble-
or byte-wide functions. Allows for mixed arithmetic
and logic functions in a single PFU.
I
Nine user registers per PFU, one following each
LUT, plus one extra. All have programmable clock
enable and local set/reset, plus a global set/reset
that can be disabled per PFU.
I
Flexible input structure (FINS) of the PFUs pro-
vides a routability enhancement for LUTs with
shared inputs and the logic flexibility of LUTs with
independent inputs.
I
Fast-carry logic and routing to adjacent PFUs for
nibble-wide, byte-wide, or longer arithmetic func-
tions, with the option to register the PFU carry-out.
I
Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
I
Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each pro-
grammable logic cell (PLC).
I
Abundant hierarchical routing resources based on
routing two data nibbles and two control lines per
set provide for faster place and route implementa-
tions and less routing delay.
I
Individually programmable drive capability: 12 mA
sink/6 mA source or 6 mA sink/3 mA source.
I
Built-in boundary scan (IEEE
1149.1 JTAG) and
testability function to 3-state all I/O pins.
I
Enhanced system clock routing for low-skew, high-
speed clocks originating on-chip or at any I/O.
I
Up to four ExpressCLK inputs allow extremely fast
clocking of signals on- and off-chip plus access to
internal general clock routing.
I
StopCLK feature to glitchlessly stop/start the
ExpressCLKs independently by user command.
* PALis a trademark of Advanced Micro Devices, Inc.
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1. Lucent Technologies’ ORCAOR3LxxxB Series FPGAs
The usable gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32
×
4 RAM
(or 512 gates) per PFU.
Device
System
Gates
120K—244K
166K—340K
LUTs
Registers
Max User
RAM
131K
185K
User I/Os
Array Size
Process
Technology
0.25 μm/5 LM
0.25 μm/5 LM
OR3L165B
OR3L225B
8192
11552
10752
14820
516
612
32
×
32
38
×
38
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OR3L225B7BC432-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BC432I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BM680-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BM680I-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B8BC432-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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