參數(shù)資料
型號： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 3/88頁
文件大小： 2015K
代理商： OR3L225B
Lucent Technologies Inc.
3
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Table of Contents
(continued)
Figure
Page
Table
Page
Figure 1. Simplified PFU Diagram...............................6
Figure 2. SLIC All Modes Diagram..............................7
Figure 3. OR3Lxxx Programmable Input/Output
Image from ORCA Foundry....................................8
Figure 4. Synchronous Memory
Write Characteristics............................................17
Figure 5. Synchronous Memory Read Cycle ............18
Figure 6. ExpressCLK to Output Delay.....................27
Figure 7. Fast Clock to Output Delay ........................28
Figure 8. System Clock to Output Delay ...................29
Figure 9. Input to ExpressCLK Setup/Hold Time ......31
Figure 10. Input to Fast Clock Setup/Hold Time........33
Figure 11. Input to System Clock Setup/Hold Time ..34
Figure 12. Package Parasitics...................................80
Table
Page
Table 1. Lucent Technologies’ ORCA
OR3LxxxB Series FPGAs......................................1
Table 2. ORCASeries 3L System Performance..........4
Table 3. Configuration Frame Size ..............................9
Table 4. General Configuration Mode Timing
Characteristics .....................................................12
Table 5. Combinatorial PFU Timing Characteristics..13
Table 6. Sequential PFU Timing Characteristics.......14
Table 7. Ripple Mode PFU Timing Characteristics....15
Table 8. Synchronous Memory
Write Characteristics............................................17
Table 9. Synchronous Memory
Read Characteristics............................................18
Table 10. PFU Output MUX and
Direct Routing Timing Characteristics..................19
Table 11. Supplemental Logic and
Interconnect Cell Timing Characteristics .............19
Table 12. Programmable I/O
Timing Characteristics .........................................20
Table 13. Microprocessor Interface (MPI) Timing
Characteristics......................................................23
Table 14. ExpressCLK (ECLK) and Fast Clock
(FCLK) Timing Characteristics ............................ 25
Table 15. General-Purpose Clock Timing
Characteristics (Internally Generated Clock)....... 26
Table 16. OR3Lxxx ExpressCLK to
Output Delay (Pin-to-Pin) .................................... 27
Table 17. OR3Lxxx Fast Clock (FCLK) to
Output Delay (Pin-to-Pin) .................................... 28
Table 18. OR3Lxxx General System Clock
(SCLK) to Output Delay (Pin-to-Pin).................... 29
Table 19. OR3Lxxx Input to ExpressCLK (ECLK)
Fast-Capture Setup/Hold Time (Pin-to-Pin)......... 30
Table 20. OR3Lxxx Input to Fast Clock
Setup/Hold Time (Pin-to-Pin)............................... 32
Table 21. OR3Lxxx Input to General System Clock
(SCLK) Setup/Hold Time (Pin-to-Pin).................. 34
Table 22. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply V
DD
) .................... 36
Table 23. Derating for Commercial/Industrial
OR3Lxxx Devices (I/O Supply V
DD
2) .................. 36
Table 24. 208-Pin SQFP2 Pinout.............................. 38
Table 25. 240-Pin SQFP2 Pinout ............................. 41
Table 26. 352-Pin PBGA Pinout................................ 44
Table 27. 432-Pin EBGA Pinout ............................... 49
Table 28. 680-Pin PBGAM Pinout............................. 60
Table 29. Absolute Maximum Ratings....................... 76
Table 30. Recommended Operating Conditions ....... 76
Table 31. Electrical Characteristics........................... 77
Table 32. Plastic Package Thermal Characteristics
for the ORCA Series............................................ 79
Table 33. Package Coplanarity ................................. 80
Table 34. Package Parasitics .................................... 80
Table 35. Voltage Options......................................... 87
Table 36. Temperature Options................................. 87
Table 37. Package Options ....................................... 87
Table 38. ORCAOR3LxxxB Series
Package Matrix.................................................... 87
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3L225B7BC432-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BC432I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BM680-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B7BM680I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3L225B8BC432-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 11552 LUT 612 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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