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參數(shù)資料
| 型號(hào)： | OR4E2 |
| 廠(chǎng)商： | Lineage Power |
| 英文描述： | Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列) |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列） |
| 文件頁(yè)數(shù)： | 1/132頁(yè) |
| 文件大?。?/td> | 2667K |
| 代理商： | OR4E2 |
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Preliminary Data Sheet
August 2000
ORCA
Series 4
Field-Programmable Gate Arrays
Programmable Features
I
High-performance platform design.
— 0.13 μm seven-level metal technology.
— Internal performance of >250 MHz
(four logic levels).
— I/O performance of >416 MHz for all user I/Os.
— Over 1.5 million usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V oper-
ation) translates to greater performance.
— Embedded block RAM (EBR) for onboard stor-
age and buffer needs.
— Built-in system components including an internal
system bus, eight PLLs, and microprocessor
interface.
I
Traditional I/O selections.
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)
I/Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability.
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-limited).
— Fast-capture input latch and input flip-flop (FF)/
latch for reduced input setup time and zero hold
time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
I
New programmable high-speed I/O.
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I & II), HSTL (Class I, III, IV), zero-bus
turn-around (ZBT*), and double data rate (DDR).
— Double-ended: LDVS, bused-LVDS, LVPECL.
— Customer defined: Ability to substitute arbitrary
standard-cell I/O to meet fast moving standards.
I
New
capability to (de)multiplex I/O signals.
— New DDR on both input and output at rates up to
311 MHz (622 MHz effective rate).
— Used to implement emerging RapidIO
back-
plane interface specification.
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 104 MHz internal to 416 MHz
I/O).
I
Enhanced twin-quad programmable function unit
(PFU).
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT and organized to allow two nibbles to act
independently, plus one extra for arithmetic
carry/borrow operations.
* ZBTis a trademark of Integrated Device Technologies Inc.
RapidIO is a trademark of Motorola, Inc.
Table 1. ORCA Series 4—Available FPGA Logic
The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The
logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic,
CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32x4 RAM (or 512
gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates are
used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are conser-
vatively utilized in the gate count calculations.
Note: Devices are not pinout compatible with ORCA Series 2/3.
Device
Columns
Rows
PFUs
User I/O
LUTs
EBR
Blocks
8
12
16
20
24
EBR Bits (k)
Usable
Gates (k)
260—470
400—720
530—970
740—1350
930—1700
OR4E2
OR4E4
OR4E6
OR4E10
OR4E14
26
36
46
60
70
24
36
44
56
66
624
1296
2024
3360
4620
400
576
720
928
1088
4992
10368
16,192
26,880
36,960
74
111
147
184
221
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