參數(shù)資料
型號： OR3L225B
廠商： Lineage Power
英文描述： Field-Programmable Gate Arrays(現(xiàn)場可編程門陣列)
中文描述： 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列）
文件頁數(shù)： 37/88頁
文件大?。?/td> 2015K
代理商： OR3L225B
Lucent Technologies Inc.
37
Data Addendum
December 1999
ORCA OR3LxxxB Series FPGAs
Estimating Power Dissipation
OR3LxxxB
The total operating power dissipated is estimated by
adding the standby (I
DDSB
), internal, and external
power dissipated. The internal and external power is
the power consumed in the PLCs and PICs, respec-
tively. In general, the standby power is small and may
be neglected. The total operating power is as follows:
P
T
=
Σ
P
PLC
+
Σ
P
PIC
The internal operating power is made up of two parts:
clock generation and PFU output power. The PFU out-
put power can be estimated based upon the number of
PFU outputs switching when driving an average fan-out
of two:
P
PFU
= 0.078 mW/MHz
For each PFU output that switches, 0.136 mW/MHz
needs to be multiplied times the frequency (in MHz)
that the output switches. Generally, this can be esti-
mated by using one-half the clock rate, multiplied by
some activity factor; for example, 20%.
The power dissipated by the clock generation circuitry
is based upon four parts: the fixed clock power, the
power/clock branch row or column, the clock power dis-
sipated in each PFU that uses this particular clock, and
the power from the subset of those PFUs that are con-
figured as synchronous memory. Therefore, the clock
power can be calculated for the four parts using the fol-
lowing equations.
OR3L165B Clock Power
P
= [0.039 mW/MHz
+ (0.046 mW/MHz/Branch) (# Branches)
+ (0.008 mW/MHz/PFU) (# PFUs)
+ (0.002 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit)
OR3L165B clock power = 9.8 mW/MHz
OR3L225B Clock Power
P
= [0.045 mW/MHz
+ (0.053 mW/MHz/Branch) (# Branches)
+ (0.008 mW/MHz/PFU) (# PFUs)
+ (0.002 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit)
OR3L225B clock power = 13.5 mW/MHz
The power dissipated in a PIC is the sum of the power
dissipated in the four PIOs in the PIC. This consists of
power dissipated by inputs and ac power dissipated by
outputs. The power dissipated in each PIO depends on
whether it is configured as an input, output, or input/
output. If a PIO is operating as an output, then there is
a power dissipation component for P
IN
, as well as
P
OUT
. This is because the output feeds back to the
input.
The power dissipated by an input buffer is (V
IH =
V
DD
–
0.3 V or higher)
estimated as:
P
IN
= 0.09 mW/MHz
The ac power dissipation from an output or bidirec-
tional is estimated by the following:
P
OUT
= (C
L
+ 8.8 pF)
×
V
DD2
×
F Watts
where the unit for C
L
is farads, and the unit for F is Hz.
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