參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 87/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Functional Overview
75
August 2002 Revised August 2003
SPRS197B
Table 338. OMAP 5910 Pin Configuration Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
FFFE:1000
FUNC_MUX_CTRL_0
Functional Multiplexing Control 0 Register
32
RW
0000 0000h
FFFE:1004
FUNC_MUX_CTRL_1
Functional Multiplexing Control 1 Register
32
RW
0000 0000h
FFFE:1008
FUNC_MUX_CTRL_2
Functional Multiplexing Control 2 Register
32
RW
0000 0000h
FFFE:100C
COMP_MODE_CTRL_0
Compatibility Mode Control 0 Register
32
RW
0000 0000h
FFFE:1010
FUNC_MUX_CTRL_3
Functional Multiplexing Control 3 Register
32
RW
0000 0000h
FFFE:1014
FUNC_MUX_CTRL_4
Functional Multiplexing Control 4 Register
32
RW
0000 0000h
FFFE:1018
FUNC_MUX_CTRL_5
Functional Multiplexing Control 5 Register
32
RW
0000 0000h
FFFE:101C
FUNC_MUX_CTRL_6
Functional Multiplexing Control 6 Register
32
RW
0000 0000h
FFFE:1020
FUNC_MUX_CTRL_7
Functional Multiplexing Control 7 Register
32
RW
0000 0000h
FFFE:1024
FUNC_MUX_CTRL_8
Functional Multiplexing Control 8 Register
32
RW
0000 0000h
FFFE:1028
FUNC_MUX_CTRL_9
Functional Multiplexing Control 9 Register
32
RW
0000 0000h
FFFE:102C
FUNC_MUX_CTRL_A
Functional Multiplexing Control A Register
32
RW
0000 0000h
FFFE:1030
FUNC_MUX_CTRL_B
Functional Multiplexing Control B Register
32
RW
0000 0000h
FFFE:1034
FUNC_MUX_CTRL_C
Functional Multiplexing Control C Register
32
RW
0000 0000h
FFFE:1038
FUNC_MUX_CTRL_D
Functional Multiplexing Control D Register
32
RW
0000 0000h
FFFE:103C
Reserved
FFFE:1040
PULL_DWN_CTRL_0
Pulldown Control 0 Register
32
RW
0000 0000h
FFFE:1044
PULL_DWN_CTRL_1
Pulldown Control 1 Register
32
RW
0000 0000h
FFFE:1048
PULL_DWN_CTRL_2
Pulldown Control 2 Register
32
RW
0000 0000h
FFFE:104C
PULL_DWN_CTRL_3
Pulldown Control 3 Register
32
RW
0000 0000h
FFFE:1050
GATE_INH_CTRL_0
Gate and Inhibit Control 0 Register
32
RW
0000 0000h
FFFE:1054
FFFE:105C
Reserved
FFFE:1060
VOLTAGE_CTRL_0
Voltage Control 0 Register
32
RW
0000 0000h
FFFE:1064
FFFE:106C
Reserved
FFFE:1070
TEST_DBG_CTRL_0
Test Debug Control 0 Register
32
RW
0000 0000h
FFFE:1074
FFFE:107C
Reserved
FFFE:1080
MOD_CONF_CTRL_0
Module Configuration Control 0 Register
32
RW
0000 0000h
Table 339. Local Bus Control Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
FFFE:C100
LB_MPU_TIMEOUT
Local bus MPU access TIMEOUT
32
RW
0000 00FFh
FFFE:C104
LB_HOLD_TIMER
Local bus hold timer
32
RW
0000 0000h
FFFE:C108
LB_PRIORITY_REG
Local bus MPU access priority
32
RW
0000 0000h
FFFE:C10C
LB_CLOCK_DIV
Local bus clock divider
32
RW
0000 00FCh
FFFE:C110
LB_ABORT_ADD
Local bus address of aborted MPU cycle
32
R
FFFF FFFFh
FFFE:C114
LB_ABORT_DATA
Local bus cycle data of aborted MPU write cycle
32
R
FFFF FFFFh
FFFE:C118
LB_ABORT_STATUS
Local bus cycle type of aborted MPU write cycle
32
R
0000 0000h
FFFE:C11C
LB_IRQ_OUTPUT
Local bus external interrupt output control
32
RW
0000 0000h
FFFE:C120
LB_IRQ_INPUT
Local bus external interrupt status
32
RW
0000 0000h
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