參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 32/160頁
文件大小： 1997K
代理商： OMAP5910(RISC)
Introduction
20
August 2002 Revised August 2003
SPRS197B
2.4
Signal Description
Table 24 provides a description of the signals on OMAP5910. Many signals are available on multiple pins
depending upon the software configuration of the pin multiplexing options. Ball numbers which are italicized
indicate the default pin muxings at reset. Ball numbers for busses are listed from MSB to LSB (left to right,
top to bottom).
Table 24. Signal Description
SIGNAL
GZG
BALL
GDY
BALL
DESCRIPTION
TYPE
EMIFF SDRAM Interface
SDRAM.WE
C3
A1
SDRAM write enable. SDRAM.WE is active (low) during writes, DCAB, and MRS
commands to SDRAM memory.
O/Z
SDRAM.RAS
A2
C4
SDRAM row address strobe. SDRAM.RAS is active (low) during ACTV, DCAB,
REFR, and MRS commands to SDRAM memory.
O/Z
SDRAM.DQMU
D4
A2
SDRAM upper data mask. Active-low data mask for the upper byte of the SDRAM
data bus (SDRAM.D[15:8]). The data mask outputs allow for both 16-bit-wide and
8-bit-wide accesses to SDRAM memories.
O/Z
SDRAM.DQML
B3
B2
SDRAM lower data mask. Active-low data mask for the lower byte of the SDRAM
data bus (SDRAM.D[7:0]). The data mask outputs allow for both 16-bit-wide and
8-bit-wide accesses to SDRAM memories.
O/Z
SDRAM.D[15:0]
D5,
C4,
B4,
D6,
C5,
H8,
C6,
B6,
D7,
C7,
D8,
B8,
G8,
C8,
G9,
B9
D4,
C5,
G8,
B4,
B5,
C6,
A3,
E6,
D6,
A4,
B6,
F7,
C7,
B7,
D7,
A6
SDRAM data bus. SDRAM.D[15:0] provides data exchange between the Traffic
Controller and SDRAM memory.
I/O/Z
SDRAM.CKE
D9
D7
SDRAM clock enable. Active-high output which enables the SDRAM clock during
normal operation; SDRAM.CKE is driven inactive to put the memory into
low-power mode.
O/Z
SDRAM.CLK
C9
A7
SDRAM clock. Clock for synchronization SDRAM memory commands/accesses.
To minimize voltage undershoot and overshoot effects, it is recommended to place
a series resistor (typically ~33
) close to the SDRAM.CLK driver pin.
I/O/Z
SDRAM.CAS
H9
F8
SDRAM column address strobe. SDRAM.CAS is active (low) during reads, writes,
and the REFR and MRS commands to SDRAM memory.
O/Z
SDRAM.BA[1:0]
D10,
C10
C9,
B8
SDRAM bank address bus. Provides the bank address to SDRAM memories.
O/Z
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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