參數(shù)資料
型號(hào)： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 111/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Functional Overview
99
August 2002 Revised August 2003
SPRS197B
3.17 Interrupts
Table 373. MPU Level 1 and Level 2 Interrupt Mappings
INTERRUPT
DEFAULT
SENSITIVITY
LEVEL 1
MAPPING
LEVEL 2
MAPPING
FUNCTION
Level 2 Interrupt handler FIQ
Level
IRQ_0
FIQ Interrupt from Level 2 Handler
CAMERA_IF_INTERRUPT
Level
IRQ_1
Camera Interface Interrupt
Reserved
IRQ_2
Reserved, keep masked
External FIQ
Edge
IRQ_3
External FIQ Interrupt
McBSP2 TX INT
Edge
IRQ_4
McBSP2 Transmit Interrupt
McBSP2 RX INT
Edge
IRQ_5
McBSP2 Receive Interrupt
IRQ_RTDX
Level
IRQ_6
Real-Time Data Exchange Interrupt
(for RTDX Emulation Tools)
IRQ_DSP_MMU_ABORT
Level
IRQ_7
DSP MMU Abort Interrupt
IRQ_HOST_INT
Level
IRQ_8
IRQ_ABORT
Level
IRQ_9
IRQ_DSP_MAILBOX1
Level
IRQ_10
DSP2ARM1 Mailbox Interrupt
IRQ_DSP_MAILBOX2
Level
IRQ_11
DSP2ARM2 Mailbox Interrupt
Reserved
IRQ_12
Reserved, keep masked
IRQ_TIPB_BRIDGE_PRIVATE
Level
IRQ_13
TIPB Private Bridge Interrupt
IRQ_GPIO
Level
IRQ_14
MPU Interrupt for MPU-owned shared GPI
IRQ_UART3
Level
IRQ_15
UART3 Interrupt
IRQ_TIMER3
Edge
IRQ_16
MPU Timer 3 Interrupt
IRQ_LB_MMU
Level
IRQ_17
Local Bus MMU Interrupt
Reserved
IRQ_18
Reserved, keep masked
IRQ_DMA_CH0_CH6
Level
IRQ_19
System DMA Channel 0 and 6 Interrupt
IRQ_DMA_CH1_CH7
Level
IRQ_20
System DMA Channel 1 and 7 Interrupt
IRQ_DMA_CH2_CH8
Level
IRQ_21
System DMA Channel 2 and 8 Interrupt
IRQ_DMA_CH3
Level
IRQ_22
System DMA Channel 3 Interrupt
IRQ_DMA_CH4
Level
IRQ_23
System DMA Channel 4 Interrupt
IRQ_DMA_CH5
Level
IRQ_24
System DMA Channel 5 Interrupt
IRQ_DMA_CH_LCD
Level
IRQ_25
System DMA LCD Channel Interrupt
IRQ_TIMER1
Edge
IRQ_26
MPU Timer 1 Interrupt
IRQ_WD_TIMER
Edge
IRQ_27
MPU Watchdog Timer Interrupt
IRQ_TIPB_BRIDGE_PUBLIC
Level
IRQ_28
TIPB Public Bridge Interrupt
IRQ_LOCAL_BUS_IF
Level
IRQ_29
Local Bus Interrupt
IRQ_TIMER2
Edge
IRQ_30
MPU Timer 2 Interrupt
IRQ_LCD_CTRL
Level
IRQ_31
LCD Controller Interrupt
FAC
Level
IRQ_0
IRQ_0
Frame Adjustment Counter Interrupt
KBD
Edge
IRQ_0
IRQ_1
Keyboard Interrupt
MICROWIRE_TX
Edge
IRQ_0
IRQ_2
Microwire Transmit Interrupt
MICROWIRE_RX
Edge
IRQ_0
IRQ_3
Microwire Receive Interrupt
I2C Interrupt
I2C
Edge
IRQ_0
IRQ_4
MPUIO
Level
IRQ_0
IRQ_5
MPUIO Interrupt
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