參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 25/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Introduction
13
August 2002 Revised August 2003
SPRS197B
Table 23. Terminal Characteristics and Multiplexing (Continued)
SUPPLY
RESET
STATE#
OTHER
BUFFER
STRENGTH
PU/
PD
§
DESELECTED
INPUT STATE
MUX CTRL
SETTING
TYPE
SIGNAL NAME
GDY
BALL
GZG
BALL
J18
G14
CAM.D[7]
I
reg4[29:27] = 000
NA
8 mA
B, J
input
ETM.D[7]
O
reg4[29:27] = 001
NA
DVDD1
UWIRE.CS0
O
reg4[29:27] = 010
NA
J19
G12
CAM.D[6]
I
reg5[2:0] = 000
NA
8 mA
B, J
input
ETM.D[6]
O
reg5[2:0] = 001
NA
DVDD1
UWIRE.CS3
O
reg5[2:0] = 010
NA
J14
H16
CAM.D[5]
I
reg5[5:3] = 000
NA
8 mA
B, J
input
ETM.D[5]
O
reg5[5:3] = 001
NA
DVDD1
UWIRE.SDI
I
reg5[5:3] = 010
NA
PD20
K18
J15
CAM.D[4]
I
reg5[8:6] = 000
NA
8 mA
B, J
input
ETM.D[4]
O
reg5[8:6] = 001
NA
DVDD8
UART3.TX
O
reg5[8:6] = 010
NA
K19
G17
CAM.D[3]
I
reg5[11:9] = 000
NA
8 mA
B, J
input
ETM.D[3]
O
reg5[11:9] = 001
NA
DVDD1
UART3.RX
I
reg5[11:9] = 010
NA
PD20
K15
H17
CAM.D[2]
I
reg5[14:12] = 000
NA
8 mA
B, J
input
ETM.D[2]
O
reg5[14:12] = 001
NA
DVDD1
UART3.CTS
I
reg5[14:12] = 010
NA
PD20
K14
H14
CAM.D[1]
I
reg5[17:15] = 000
NA
8 mA
B, J
input
ETM.D[1]
O
reg5[17:15] = 001
NA
DVDD1
UART3.RTS
O
reg5[17:15] = 010
NA
L19
J16
CAM.D[0]
I
reg5[20:18] = 000
NA
8 mA
B, J
input
ETM.D[0]
O
reg5[20:18] = 001
NA
DVDD1
MPUIO12
I/O/Z
reg5[20:18] = 010
NA
L18
J17
CAM.VS
I
reg5[23:21] = 000
NA
8 mA
B, J
input
ETM.PSTAT[2]
O
reg5[23:21] = 001
NA
DVDD1
L15
K15
CAM.HS
I
reg5[26:24] = 000
NA
8 mA
B, J
input
ETM.PSTAT[1]
O
reg5[26:24] = 001
NA
DVDD1
UART2.CTS
I
reg5[26:24] = 010
NA
PD20
M19
J14
CAM.RSTZ
O
reg5[29:27] = 000
NA
8 mA
J, B, G1
0
ETM.PSTAT[0]
O
reg5[29:27] = 001
NA
DVDD1
UART2.RTS
O
reg5[29:27] = 010
NA
M18
J13
pin forced to drive low
O
reg6[2:0] = 000
NA
4 mA
J, A, G1
0
UART3.TX
O
reg6[2:0] = 001
NA
DVDD1
PWT
O
reg6[2:0] = 010
NA
IRQ_OBS
O
reg6[2:0] = 011
NA
UART2.TX
O
reg6[2:0] = 100
NA
I = Input, O = Output, Z = High-Impedance
’regx’ denotes the terminal multiplexing register that controls the specified terminal where regx = FUNC_MUX_CTRL_x
§PD20 = 20-
μ
A internal pulldown, PD100 = 100-
μ
A pulldown, PU20 = 20-
μ
A internal pullup, PU100 = 100-
μ
A internal pullup
A = Standard LVCMOS input/output
B = Fail-safe LVCMOS input/output
C = USB transceiver input/output
D = I2C input/output buffers
E = Fail-safe LVCMOS input and Standard LVCMOS output
F = analog oscillator terminals
#Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low
|| UART1 signals can be multiplexed to this pin via additional multiplexing in the USB module.
G1 = Terminal may be gated by BFAIL
G2 = Terminal may be gated by GPIO9 and MPUIO3
G3 = Terminal may be gated by BFAIL and PWRON_RESET
H1 = Terminal may be 3-stated by BFAIL input
J = Boundary-scannable terminal
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