參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 108/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Functional Overview
96
August 2002 Revised August 2003
SPRS197B
Table 369. UART2 Registers
DSP WORD
ADDRESS
MPU BYTE
ADDRESS
MPU BYTE
ADDRESS
(VIA MPUI)
REGISTER
NAME
DESCRIPTION
ACCESS
WIDTH
ACCESS
TYPE
RESET
VALUE
0x00 8400h
FFFB:0800
E101:0800
UART2_RHR
UART2_THR
UART2_DLL§
UART2_IER
UART2_DLH§
UART2 receive holding register
8
R
Undefined
0x00 8400h
FFFB:0800
E101:0800
UART2 transmit holding register
8
W
Undefined
0x00 8400h
FFFB:0800
E101:0800
UART2 divisor latch low register
8
RW
00h
0x00 8401h
FFFB:0804
E101:0802
UART2 interrupt enable register
8
RW
00h
0x00 8401h
FFFB:0804
E101:0802
UART2 divisor latch high register
8
RW
00h
0x00 8402h
FFFB:0808
E101:0804
UART2_IIR
UART2 interrupt identification
register
8
R
01h
0x00 8402h
FFFB:0808
E101:0804
UART2_FCR
UART2_EFR§
UART2 FIFO control register
8
W
00h
0x00 8402h
FFFB:0808
E101:0804
UART2 enhanced feature register
8
RW
00h
0x00 8403h
FFFB:080C
E101:0806
UART2_LCR
UART2_MCR
UART2_XON1§
UART2_LSR
UART2_XON2§
UART2_MSR
UART2_TCR#
UART2_XOFF1§
UART2_SPR
UART2_TLR#
UART2_XOFF2§
UART2 line control register
8
RW
00h
0x00 8404h
FFFB:0810
E101:0808
UART2 modem control register
8
RW
00h
0x00 8404h
FFFB:0810
E101:0808
UART2 XON1 register
8
RW
00h
0x00 8405h
FFFB:0814
E101:080A
UART2 mode register
8
R
60h
0x00 8405h
FFFB:0814
E101:080A
UART2 XON2 register
8
RW
00h
0x00 8406h
FFFB:0818
E101:080C
UART2 modem status register
8
R
Undefined
0x00 8406h
FFFB:0818
E101:080C
UART2 transmission control register
8
RW
0Fh
0x00 8406h
FFFB:0818
E101:080C
UART2 XOFF1 register
8
RW
00h
0x00 8407h
FFFB:081C
E101:080E
UART2 scratchpad register
8
RW
00h
0x00 8407h
FFFB:081C
E101:080E
UART2 trigger level register
8
RW
00h
0x00 8407h
FFFB:081C
E101:080E
UART2 XOFF2 register
8
RW
00h
0x00 8408h
FFFB:0820
E101:0810
UART2_MDR1
UART2 mode definition 1 register
8
RW
07h
0x00 8409
0x00840Dh
FFFB:0824
FFFB:0834
Reserved
0x00 840Eh
FFFB:0838
E101:081C
UART2_UASR§
UART2 autobauding status register
8
R
00h
0x00 840Fh
FFFB:083C
Reserved
0x00 8410h
FFFB:0840
E101:0820
UART2_SCR
UART2 supplementary control
register
8
RW
00h
0x00 8411h
FFFB:0844
E101:0822
UART2_SSR
UART2 supplementary status
register
8
R
00h
0x00 8412h
FFFB:0848
Reserved
0x00 8413h
FFFB:084C
E101:0826
UART2_OSC_
12M_SELV
UART2 12-/13-MHz oscillator select
register
8
W
00h
0x00 8414h
Register is accessible when LCR[7] = 0 (normal operating mode)
Register is accessible when LCR[7] = 1 and LCR[7:0]
§Register is accessible when LCR[7] = 0BFh
Register is write accessible when EFR[4] = 1
#Register is accessible when EFR[4] = 1 and MCR[6] = 1
FFFB:0850
E101:0828
UART2_MVR
UART2 module version register
8
R
0BFh
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