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| 型號(hào)： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁數(shù)： | 65/160頁 |
| 文件大小： | 1997K |
| 代理商： | OMAP5910(RISC) |
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Functional Overview
53
August 2002 Revised August 2003
SPRS197B
3.12 Interprocessor Communication
Several mechanisms allow for communication between the MPU and the DSP on the OMAP5910 device.
These include mailbox registers, MPU Interface, and shared memory space.
3.12.1
MPU/DSP Mailbox Registers
The MPU and DSP processors may communicate with each other via a mailbox-interrupt mechanism. This
mechanism provides a very flexible software protocol between the processors. There are four sets of mailbox
registers located in public TIPB space. The registers are shared between the two processors, so the MPU and
DSP may both access these registers within their own public TIPB space, but read/write accessibility of each
register is different for each processor.
There are four sets of mailbox registers: two for the MPU to send messages and issue an interrupt to the DSP,
the other two for the DSP to send messages and issue an interrupt to the MPU. Each set of mailbox registers
consists of two 16-bit registers and a 1-bit flag register. The interrupting processor can use one 16-bit register
to pass a data word to the interrupted processor and the other 16-bit register to pass a command word.
Communication is achieved when one processor writes to the appropriate command word register which
causes an interrupt to the other processor and sets the appropriate flag register. The interrupted processor
acknowledges by reading the command word which causes the flag register to be cleared. An additional
data-word register is also available in each mailbox register set to optionally communicate two words of data
between the processors for each interrupt instead of just communicating the command word.
The information communicated by the command and data words are entirely user-defined. The data word may
be optionally used to indicate an address pointer or status word.
3.12.2
MPU Interface (MPUI)
The MPU interface (MPUI) allows the MPU and the system DMA controller to communicate with the DSP and
its peripherals. The MPUI allows access to the full memory space (16M bytes) of the DSP and the DSP public
peripheral bus. Thus, the MPU and System DMA Controller both have read and write access to the complete
DSP I/O space (128K bytes), including the control registers of the DSP public peripherals.
The MPUI port supports the following features:
Four access modes:
Shared-access mode (SAM) for MPU access of DSP SARAM, DARAM, and external memory
interface
Shared-access mode (SAM) for peripheral bus access
Host-only mode (HOM) for SARAM access
Host-only mode (HOM) for peripheral bus access
Interrupt to MPU if access time-out occurs
Programmable priority scheme (MPU vs. DMA)
Packing and unpacking of data (16 bits to 32 bits, and vice versa)
32-bit single access support
Software control endianism conversion
System DMA capability to full DSP memory space (16M bytes)
System DMA capability to the DSP public TIPB peripherals (up to 128K bytes space)
This port can be used for many functions, such as: MPU loading of program code into DSP program memory
space, sharing of data between MPU and DSP, implementing interprocessing communication protocols via
shared memory, or allowing MPU to use and control DSP Public TIPB Peripherals.
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| OMAP5912ZDY | 功能描述:處理器 - 專門應(yīng)用 Applications Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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