參數(shù)資料
型號(hào)： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 43/160頁
文件大小： 1997K
代理商： OMAP5910(RISC)
Introduction
31
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
Interrupts and Miscellaneous Control and Configuration Pins (Continued)
STAT_VAL/WKUP
Y17
U14
Static Valid / Chip wake-up input. STAT_VAL/WKUP may be configured via
software to function as an external wake-up signal to the OMAP5910 device to
request chip wake-up during sleep modes. STAT_VAL/WKUP is also sampled at
reset to select the MMC/SD port. If the MMC/SD peripheral is to be used, this pin
must be pulled high during reset. It is recommended that this pin be pulled high
during reset regardless of whether or not MMC/SD will be used.
I
RST_HOST_OUT
P14
U13
Reset Host output. A software controllable Reset or Shutdown output to an
external device.
O
RSVD
E5
N11
Reserved pin. This pin must be left unconnected.
Power Supplies
VSS§
A21,
B1,
B2,
B5,
B7,
B16,
B18,
E2,
F20,
G1,
J20,
K2,
K20,
N1,
R21,
U2,
U20,
V5,
V12,
W20,
Y3,
Y15,
AA1,
AA7,
AA21
N5,
H8,
G11,
M6,
L11,
K8,
J12,
J9,
G7,
E5,
J7,
J8,
J6,
J10,
K10,
H10,
F12,
L7,
F6,
L9,
K9,
M12,
E13,
J11,
N13
Ground. Common ground return for all core and I/O voltage supplies.
power
CVDD
A9,
F2,
P12,
Y20
E8,
E2,
T17,
P10
Core supply voltage. Supplies power to OMAP5910 core logic and low-voltage
sections of I/O.
power
CVDD1
A3
B3
Core Supply Voltage 1. Supplies power to the on-chip shared SRAM memory
(192k-Bytes).
power
CVDD2
Y1,
AA3
K7,
L8
Core Supply Voltage 2. Supplies power to the MPU subsystem logic and memory.
power
CVDD3
B13,
B20,
J21,
R20
F10,
G10,
H11,
K11
Core Supply Voltage 3. Supplies power to the DSP subsystem logic and memory.
power
CVDD4
M2
K2
Core Supply Voltage 4. Supplies power to the DPLL which provides internal clocks
to the core and peripherals (excluding USB peripherals).
NOTE:
The voltage to
this supply pin should be kept as clean as possible to maximize performance.
power
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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