參數(shù)資料
型號(hào)： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 153/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Electrical Specifications
141
August 2002 Revised August 2003
SPRS197B
5.16 Microwire Interface Timings
Table 532 and Table 533 assume testing over recommended operating conditions (see Figure 535).
Table 532. Microwire Timing Requirements
NO.
MIN
MAX
UNIT
W5
tsu(SDISCLK)
th(SCLKSDI)
Setup time, UWIRE.SDI valid before UWIRE.SCLK active edge
Hold time, UWIRE.SDI invalid after UWIRE.SCLK active edge
Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software
configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data
and capture input data.
21
ns
W6
6
ns
Table 533. Microwire Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
W1
fop(SCLK)
tw(SCLK)
td(SCLKSDO)
td(CSSCLK)
Operating Frequency, UWIRE.SCLK
3
MHz
W2
Pulse Duration, UWIRE.SCLK high/low
Delay time, UWIRE.SCLK active edge to UWIRE.SDO transition
Delay time, UWIRE.CSx active to UWIRE.SCLK active
Polarity of UWIRE.SCLK and the active clock edge (rising or falling) on which SDO data is driven and SDI data is latched is all software
configurable. These timings apply to all configurations regardless of UWIRE.SCLK polarity and which clock edges are used to drive output data
and capture input data.
P = UWIRE.SCLK cycle time in ns.
0.45P
0.55P
ns
W3
3
6
ns
W4
1.5P
ns
UWIRE.SCLK
UWIRE.CSx
W2
W2
UWIRE.SDO
W3
[1/W1]
UWIRE.SDI
Valid
Valid
Valid
Valid
Valid
Valid
W3
W5
W6
W4
W4
NOTE: The polarities of UWIRE.CSx and UWIRE.SCLK and the active UWIRE.SCLK edges on which SDO is driven and SDI is sampled are all
software configurable.
Figure 535. Microwire Timings
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