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| 型號(hào)： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁(yè)數(shù)： | 42/160頁(yè) |
| 文件大?。?/td> | 1997K |
| 代理商： | OMAP5910(RISC) |
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Introduction
30
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
Device Clock Pins (Continued)
OSC1_OUT
W3
P3
Base crystal XO connection. Analog output from base oscillator for use with
external 12- or 13-MHz crystal.
analog
MCLK
Y9
U7
M-Clock. General-purpose clock output which may be configured to run at 12 MHz
or 48 MHz. MCLK may be configured to drive constantly or only when the
MCLKREQ signal is asserted active high.
O
BCLK
Y13
P11
B-Clock. General purpose clock output which may be configured to run at
12 MHz. BCLK may be configured to drive constantly or only when the BCLKREQ
signal is asserted active high.
O
MCLKREQ
R10
N8
M-Clock Request. Active high request input which allows an external device to
request that MCLK be driven.
I
BCLKREQ
R13
L10
B-Clock Request. Active high request input which allows an external device to
request that BCLK be driven.
I
Reset Logic Pins
PWRON_RESET
G19
F14
Reset input to device. Active-low asynchronous reset input resets the entire
OMAP5910 device.
I
MPU_RST
V15
P12
MPU reset input. Active-low asynchronous reset input resets the MPU core.
I
RST_OUT
W15
M11
Reset output. Active-low output is asserted when MPUST is active (after
synchronization.)
O
Interrupts and Miscellaneous Control and Configuration Pins
MPU_BOOT
AA17
R12
MPU boot mode. When MPU_BOOT is low, the MPU boots from chip select 0 of
the EMIFS (Flash) interface. When MPU_BOOT is high, the MPU boots from chip
select 3 of EMIFS.
I
DMA_REQ_OBS
L14
H12
DMA request external observation output.
O
IRQ_OBS
M18
J13
IRQ external observation output.
O
EXT_DMA_REQ1
T19
N15
External DMA requests. EXT_DMA_REQ0 and EXT_DMA_REQ1 provide two
DMA request inputs which external devices may use to trigger System DMA
transfers. The System DMA must be configured in software to respond to these
external requests.
I
EXT_DMA_REQ0
N15
N17
BFAIL/EXT_FIQ
W19
R14
Battery power failure and external FIQ interrupt input. BFAIL/EXT_FIQ may be
used to gate certain input pins when battery power is low or failing. The pins which
may be gated are configured via software. This pin can also optionally be used as
an external FIQ interrupt source to the MPU. The function of this pin is
configurable via software.
I
EXT_MASTER_REQ
R10
N8
External master request. If the 12-MHz clock is provided by an external device
instead of using the on-chip oscillator, a high level on this output indicates to the
external device that the clock must be driven. A low level indicates that the
OMAP5910 device is in sleep mode and the 12-MHz clock is not necessary.
O
LOW_PWR
T20
L13
Low-power request output. This active-high output indicates that the OMAP5910
device is in a low-power sleep mode. During reset and functional modes,
LOW_PWR is driven low. This signal can be used to indicate a low-power state to
external power management devices in a system or it can be used as a chip
select to external SDRAM memory to minimize current consumption while the
SDRAM is in self-refresh and the OMAP5910 device is in sleep mode.
O
CONF
V18
T16
Configuration input. CONF selects reserved factory test modes. CONF should
always be pulled low during device operation.
I
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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