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| 型號： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁數(shù)： | 64/160頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | OMAP5910(RISC) |
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Functional Overview
52
August 2002 Revised August 2003
SPRS197B
3.10 DSP DMA Controller
The DSP subsystem has its own dedicated DMA Controller, which is entirely independent of the MPU or the
System DMA Controller. The DSP DMA Controller has many of the same major features that the System DMA
Controller possesses (see Section 3.9).
The DSP DMA Controller has six generic channels and five physical ports available for source or destination
data. These five ports are the SARAM port, DARAM port, EMIF (External memory port), DSP TIPB port, and
MPUI port. The DSP may configure the DSP DMA Controller to transfer data between the SARAM, DARAM,
EMIF, and TIPB ports, but the MPUI port is a dedicated port used for MPU or System DMA initiated transfers
to DSP subsystem resources. The SARAM and DARAM ports are used to access local DSP memories and
the TIPB port is used to access the registers of the DSP peripherals. The EMIF port of the DSP DMA controller
is used to access the Traffic Controller via the DSP MMU (Memory Management Unit).
3.11 Traffic Controller (Memory Interfaces)
The Traffic Controller (TC) manages all accesses by the MPU, DSP, System DMA, and Local Bus to the
OMAP5910 system memory resources. The TC provides access to three different memory interfaces:
External Memory Interface Slow (EMIFS), External Memory Interface Fast (EMIFF), and Internal Memory
Interface (IMIF). The IMIF allows access to the 192K bytes of on-chip SRAM.
The EMIFS Interface provides 16-bit-wide access to asynchronous or synchronous memories or devices,
including the following:
Intel
fast boot block flash (23FxxxF3)
AMD
simultaneous read/write boot sector flash (AM29DLxxxG)
AMD burst-mode flash (AM29BLxxxC)
Intel StrataFlash
memory (28FxxxJ3A)
Intel synchronous StrataFlash memory (28FxxxK3/K18)
Intel wireless flash memory (28FxxxW18)
Asynchronous SRAM
The EMIFF Interface provides access to 16-bit-wide access to standard SDRAM memories and the IMIF
provides access to the 192K bytes of on-chip SRAM.
The TC provides the functions of arbitrating contending accesses to the same memory interface from different
initiators (MPU, DSP, System DMA, Local Bus), synchronization of accesses due to the initiators and the
memory interfaces running at different clock rates, and the buffering of data allowing burst access for more
efficient multiplexing of transfers from multiple initiators to the memory interfaces.
The TC’s architecture allows simultaneous transfers between initiators and different memory interfaces
without penalty. For instance, if the MPU is accessing the EMIFF at the same time, the DSP is accessing the
IMIF, transfers may occur simultaneously since there is no contention for resources. There are three separate
ports to the TC from the System DMA (one for each of the memory interfaces), allowing for greater bandwidth
capability between the System DMA and the TC.
Intel and Intel StrataFlash are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
AMD is a trademark of Advanced Micro Devices, Inc.
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