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| 型號(hào)： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁(yè)數(shù)： | 40/160頁(yè) |
| 文件大?。?/td> | 1997K |
| 代理商： | OMAP5910(RISC) |
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Introduction
28
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
Multichannel Serial Interfaces (MCSIs) (Continued)
MCSI1.DIN
W13
R10
MCSI data in. Multichannel Serial Interface data input pin.
I
MCSI2.DIN
AA9
P8
MCSI1.DOUT
W14
N12
MCSI data out. Multichannel Serial Interface data output pin.
O
MCSI2.DOUT
W9
T7
USB (Integrated Transceiver Interface, can be used with Host or Function)
USB.DP
P9
P5
USB internal transceiver D+. The positive side of the integrated USB transceiver’s
differential bus. A series resistor of 27
(5% tolerance) is required on the
USB.DP pin.
I/O/Z
USB.DM
R8
P4
USB internal transceiver D. The negative side of the integrated USB
transceiver’s differential bus. A series resistor of 27
(5% tolerance) is required
on the USB.DM pin.
I/O/Z
USB Pin Group 1 and 2 (Utilizing External Transceivers, can be used with Host or Function)
USB2.TXEN
W9
T7
USB transmit data. Single-ended logic output used to transmit data to the transmit
USB2.TXD
V6
R4
device.
USB1.TXEN
W16
T6
O
USB transmit enable. Driven active (high) when the USB host or Function
peripheral is driving data onto the USB bus via the TXD output.
USB1.TXD
W14
N12
O
input of an external USB transceiver. USBx.TXD may also be used for
transceiverless connection between OMAP5910 and another transceiverless USB
USB1.VP
V13
T11
USB vplus data. Single-ended input used to monitor the logical state of the D+ line
of the USB bus. USBx.VP should be driven by an external USB transceiver based
on the state of D+.
I
USB2.VP
AA9
P8
USB1.VM
AA13
U11
USB vminus data. Single-ended input used to monitor the logical state of the D
line of the USB bus. USBx.VM should be driven by an external USB transceiver
based on the state of D.
I
USB2.VM
R9
M7
USB1.RCV
W13
R10
USB receive data. Single-ended logic input used to receive data from the receive
output of an external USB transceiver. USBx.RCV may also be used for
transceiverless connection between OMAP5910 and another transceiverless USB
device.
I
USB2.RCV
Y5
N6
USB1.SUSP
AA17
R12
USB bus segment suspend control. Active-high output indicates detection of IDLE
condition on the USB bus for greater than 5 ms. USBx.SUSP is implemented on
both USB ports 1 and 2.
O
USB2.SUSP
Y10
T8
USB1.SE0
P14
U13
zero state on the USB bus. USBx.SE0 is implemented for both USB ports 1 and 2.
O
USB2.SE0
W5
U4
USB single-ended zero. Active-high output indicates detection of the single-ended
USB1.SPEED
Y12
N10
USB 1 bus segment speed control. Static control output used by the external
transceiver to determine whether USB port 1 is operating in full-speed or
low-speed mode. USB1.SPEED is only implemented on USB port 1.
O
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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| OMAP5912ZDY | 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 Applications Processor RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| OMAP5912ZDYA | 制造商:Texas Instruments 功能描述:APPLICATIONS PROCESSOR - Trays |
| OMAP5912ZZG | 功能描述:處理器 - 專(zhuān)門(mén)應(yīng)用 Applications Processor RoHS:否 制造商:Freescale Semiconductor 類(lèi)型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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