參數(shù)資料
型號(hào): OMAP5910(RISC)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 123/160頁
文件大小: 1997K
代理商: OMAP5910(RISC)
Electrical Specifications
111
August 2002 Revised August 2003
SPRS197B
5.7
Reset Timings
This section provides the timing requirements for the OMAP5910 hardware reset signals.
5.7.1 OMAP5910 Device Reset
The PWRON_RESET signal is the active-low asynchronous reset input responsible for the reset of the entire
OMAP5910 device. When using an external crystal to supply the 32-kHz system clock, PWRON_RESET must
be asserted low a minimum of two 32-kHz clock cycles longer than the worst-case start-up time of the 32-kHz
oscillator after stable power supplies (see Figure 55). If an external CMOS input signal is used to source
32 kHz, PWRON_RESET must be asserted low a minimum of two 32-kHz clock cycles after stable power
supplies. See Table 56 and Table 57.
Table 56. OMAP5910 Device Reset Timing Requirements
NO.
MIN
MAX
UNIT
RS1
tw(PWRON_RST)
Pulse duration, PWRON_RESET low
800
ms
Table 57. OMAP5910 Device Reset Switching Characteristics
NO.
PARAMETER
MIN
MAX
UNIT
μ
s
RS2
td(PWRONH-RSTH)
Delay time, PWRON_RESET high to RST_OUT high
T + 10
P = period of 32-kHz clock, C = Value of ULPD wakeup time setup register, SETUP_ULPD1_REG (Default 03FFh), T = P*C
CVDDx
DVDDx
OSC32K_IN
PWRON_RESET
RS1
RST_OUT
RS2
Worst-case Oscillator Start-up Time
2 Cycles
Figure 55. Device Reset Timings
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