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| 型號(hào)： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁數(shù)： | 55/160頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | OMAP5910(RISC) |
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Functional Overview
43
August 2002 Revised August 2003
SPRS197B
3.5
MPU and DSP Private Peripherals
The MPU and DSP each have their own separate private peripheral bus. Peripherals on each of these private
buses may only be accessed by their respective processors. For instance, the DSP timers on the DSP private
peripheral bus are not accessible by the MPU or the System DMA controller.
3.5.1 Timers
The MPU and DSP each have their own three 32-bit timers available on their respective private TI Peripheral
Bus (TIPB). These timers are used by the operating systems to provide general-purpose housekeeping
functions, or in the case of the DSP, to also provide synchronization of real-time processing functions. These
timers may be configured either in auto-reload or one-shot mode with on-the-fly read capability. The timers
generate an interrupt to the respective processor (MPU or DSP) when the timer’s down-counter is equal to
zero.
3.5.2 32k Timer (MPU only)
The MPU has one 32k Timer that runs on the 32-kHz clock as opposed to the MPU subsystem domain clock.
The MPU subsystem operating system (OS) requires interrupts at regular time intervals for OS scheduling
purpose (typically 1 ms to 30 ms). These time intervals can be generated using the MPU’s three 32-bit
general-purpose timers. However, these timers cannot be used in sleep modes when the system clock is not
operating. Therefore, a 32-kHz clock-based timer is needed to provide the required OS timing interval.
3.5.3 Watchdog Timer
The MPU and DSP each have a single Watchdog Timer. Each watchdog timer can be configured as either
a watchdog timer or a general-purpose timer.
A watchdog timer requires that the MPU or DSP software or OS periodically write to the appropriate WDT count
register before the counter underflows. If the counter underflows, the WDT generates a reset to the
appropriate processor (MPU or DSP). The DSP WDT resets only the DSP processor while the MPU WDT
resets both processors (MPU and DSP). The watchdog timers are useful for detecting user programs that are
stuck in an infinite loop, resulting in loss of program control or in a runaway condition.
When used as a general-purpose timer, the WDT is a 16-bit timer configurable either in autoreload or one-shot
mode with on-the-fly read capability. The timer generates an interrupt to the respective processor (MPU or
DSP) when the timer’s down-counter is equal to zero.
3.5.4 Interrupt Handlers
The MPU and DSP each have two levels of interrupt handling, allowing up to 39 interrupts to the DSP and
63 interrupts to the MPU.
3.5.5 LCD Controller
The OMAP5910 device includes an LCD Controller that interfaces with most industry-standard LCDs. The
LCD Controller is configured by the MPU and utilizes a dedicated channel on the System DMA to transfer data
from the frame buffer. The frame buffer can be implemented using the internal shared SRAM (192K bytes)
or optionally using external SDRAM via the EMIFF. Using the frame buffer as its data source, the System DMA
must provide data to the FIFO at the front end of the LCD controller data path at a rate sufficient to support
the chosen display mode and resolution. Optimal performance is achieved when using the internal SRAM as
the frame buffer.
The panel size is programmable, and can be any width (line length) from 16 to 1024 pixels in 16-pixel
increments. The number of lines is set by programming the total number of pixels in the LCD. The total frame
size is programmable up to 1024 x 1024. However, frame sizes and frame rates supported in specific
applications will depend upon the available memory bandwidth allowed by the specific application as well as
the maximum configurable pixel clock rate.
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| OMAP5912ZDY | 功能描述:處理器 - 專門應(yīng)用 Applications Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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| OMAP5912ZZG | 功能描述:處理器 - 專門應(yīng)用 Applications Processor RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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