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| 型號(hào)： | OMAP5910(RISC) |
| 英文描述： | Dual-Core Processor |
| 中文描述： | 雙核處理器 |
| 文件頁(yè)數(shù)： | 66/160頁(yè) |
| 文件大?。?/td> | 1997K |
| 代理商： | OMAP5910(RISC) |
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Functional Overview
54
August 2002 Revised August 2003
SPRS197B
3.12.3
MPU/DSP Shared Memory
The OMAP5910 device implements a shared memory architecture via the Traffic Controller. Therefore, the
MPU and DSP both have access to the same shared SRAM memory (192K bytes) as well as to the EMIFF
and EMIFS memory space. Through the DSP Memory Management Unit (MMU), the MPU controls which
regions of shared memory space the DSP is allowed to access. By setting up regions of shared memory, and
defining a protocol for the MPU and DSP to access this shared memory, an interprocessor communication
mechanism may be implemented. This method may be used in conjunction with the mailbox registers to create
handshaking interrupts which will properly synchronize the MPU and DSP accesses to shared memory.
Utilizing the shared memory in this fashion may be useful when the desired data to be passed between the
MPU and DSP is larger than the two 16-bit words provided by each set of mailbox command and data registers.
For example, the MPU may need to provide the DSP with a list of pointers to perform a specific task as opposed
to a single command and single pointer. Using shared memory and the mailboxes, the DSP could read the
list of pointers from shared memory after receiving the interrupt caused by an MPU write to the mailbox
command register.
3.13 DSP Hardware Accelerators
The TMS320C55x DSP core within the OMAP5910 device utilizes three powerful hardware accelerator
modules which assist the DSP core in implementing specific algorithms that are commonly used in video
compression applications such as MPEG4 encoders/decoders. These accelerators allow implementation of
such algorithms using fewer DSP instruction cycles and dissipating less power than implementations using
only the DSP core. The hardware accelerators are utilized via functions from the TMS320C55x Image/Video
Processing Library available from Texas Instruments.
Utilizing the hardware accelerators, the Texas Instruments Image/Video Processing Library implements many
useful functions, which include the following:
Forward and Inverse Discrete Cosine Transform (DCT) (used for video compression/decompression)
Motion Estimation (used for compression standards such as MPEG video encoding and H.26x encoding)
Pixel Interpolation (enabling high-performance fractal-pixel motion estimation)
Quantization/Dequantization (useful for JPEG, MPEG, H.26x Encoding/Decoding)
Flexible 1D/2D Wavelet Processing (useful for JPEG2000, MPEG4, and other compression standards)
Boundary and Perimeter Computation (useful for Machine Vision applications)
Image Threshold and Histogram Computations (useful for various Image Analysis applications)
3.13.1
DCT/iDCT Accelerator
The DCT/iDCT hardware accelerator is used to implement Forward and Inverse DCT (Discrete Cosine
Transform) algorithms. These DCT/iDCT algorithms can be used to implement a wide range of video
compression standards including JPEG Encode/Decode, MPEG Video Encode/Decode, and H.26x
Encode/Decode.
3.13.2
Motion Estimation Accelerator
The Motion Estimation hardware accelerator implements a high-performance motion estimation algorithm,
enabling MPEG Video encoder or H.26x encoder applications. Motion estimation is typically one of the most
computation-intensive operations in video-encoding systems.
3.13.3
Pixel Interpolation Accelerator
The Pixel Interpolation Accelerator enables high-performance pixel-interpolation algorithms, which allows for
powerful fractal pixel motion estimation when used in conjunction with the Motion Estimation accelerator. Such
algorithms provide significant improvement to video-encoding applications.
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