參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 37/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Introduction
25
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
ETM9 Trace Macro Interface (Continued)
ETM.PSTAT[2:0]
L18,
L15,
M19
J17,
K15,
J14
ETM9 Trace Pipe State 20. Pipeline status outputs for standard ETM9 test/debug
equipment.
O
Microwire Interface
UWIRE.SCLK
V19,
J15
M13,
H15
Microwire serial clock. This pin drives a clock to a Microwire device. The active
edge is software configurable.
O
UWIRE.SDO
W21,
H19
P16,
G13
Microwire serial data out. Write data is transferred to a Microwire device on this
pin.
O
UWIRE.SDI
U18,
J14
P17,
H16
Microwire serial data in. Read data is transferred from a Microwire device on this
pin.
I
UWIRE.CS0
N14,
J18
R16,
G14
Microwire chip select 0. The CS0 output selects a single Microwire device
(configurable as active high or active low).
O
UWIRE.CS3
P15,
J19
L12,
G12
Microwire chip select 3. The CS3 output selects a single Microwire device
(configurable as active high or active low).
O
HDQ/1-Wire Interface
HDQ
N20
L16
HDQ/1-wire interface. HDQ optionally implements one of two serial protocols:
HDQ or 1-Wire.
I/O
General-Purpose I/O (GPIO) and MPU I/O (MPUIO)
GPIO15
M20
K16
or the MPU core. Control of each GPIO pin between the two cores is selected by
the MPU via control registers. Each GPIO pin may also be configured to cause an
interrupt to its respective core processor.
I/O/Z
GPIO14
N21
K17
Shared General-Purpose I/O. Each GPIO pin can be used by either the DSP core
GPIO13
N19
K14
GPIO12
N18,
W6
L15,
P6
GPIO5 and GPIO10 are not available on the OMAP5910 device.
GPIO11
N20,
V7
L16,
T5
GPIO9
W8
M8
GPIO8
Y8
U6
GPIO7
M15,
Y5,
V9
L17,
N6,
R7
GPIO6
P19
K13
GPIO4
P20
L14
GPIO3
P18
K12
GPIO2
M14
M15
GPIO1
R19
M17
GPIO0
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
R18
M16
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