參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 38/160頁
文件大小： 1997K
代理商： OMAP5910(RISC)
Introduction
26
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
General-Purpose I/O (GPIO) and MPU I/O (MPUIO) (Continued)
MPUIO12
L19
J16
MPU General-Purpose I/O. MPUIO pins may only be used by the MPU core.
I/O/Z
MPUIO11
W10
R8
MPUIO8, MPUIO9, AND MPUIO10 are not available on the OMAP5910 device.
MPUIO7
V10
M9
MPUIO6
W11
R9
MPUIO5
T20,
W5
L13,
U4
MPUIO4
T19
N15
MPUIO3
V8
P7
MPUIO2
N15
N17
MPUIO1
U19
M14
MPUIO0
Y12
N10
Pulse-Width Tone and Pulse-Width Light Interface
PWT
M18
J13
Pulse Width Tone output. The PWT output pin provides a modulated output for use
with an external buzzer.
O
PWL
L14
H12
Pulse Width Light output. The PWL output pin provides a pseudo-random
modulated voltage output used for LCD or keypad backlighting.
O
Multimedia Card/Secure Digital Interface (MMC/SD)
MMC.CLK
V11
U10
MMC/SD clock. Clock output to the MMC/SD card.
O
MMC.CMD/SPI.DO
P11
U8
MMC/SD command / SPI data output. MMC/SD commands are transferred to/from
this pin. The pin functions as the data output during SPI mode.
I/O/Z
MMC.DAT3
W11
R9
SD card data bit 3. Data bit 3 used in 4-bit Secure Digital mode.
I/O/Z
MMC.DAT2
W10,
M15
R8,
L17
SD card data bit 2. Data bit 2 used in 4-bit Secure Digital mode.
I/O/Z
MMC.DAT1
V10
M9
SD card data bit 1. Data bit 1 used in 4 -bit Secure Digital mode.
I/O/Z
MMC.DAT0/SPI.DI
R11
U9
MMC/SD dat0 / SPI input. MMC.DAT0/SPI.DI functions as data bit 0 during MMC
and Secure Digital operation. The pin functions as the data input in generic SPI
mode.
I/O/Z
SPI.CLK
M14
M15
SPI clock. SPI clock output used during generic SPI mode operation.
SPI chip selects. SPI chip selects used during generic SPI mode operation.
O
O
SPI.CS3
P18
K12
SPI.CS2
P20
L14
SPI.CS1
P19
K13
SPI.RDY
R18
M16
SPI ready. SPI ready input from SPI device used only in generic SPI mode
operation.
I
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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