參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 36/160頁
文件大?。?/td> 1997K
代理商： OMAP5910(RISC)
Introduction
24
August 2002 Revised August 2003
SPRS197B
Table 24. Signal Description (Continued)
GDY
BALL
SIGNAL
TYPE
DESCRIPTION
GZG
BALL
Multichannel Buffered Serial Ports (McBSPs) (Continued)
MCBSP1.DX
H18,
H15
F16,
F17
McBSP transmit data. Serial transmit data output. DX is present on all McBSPs.
O
MCBSP2.DX
AA5,
P10
R5,
R6
MCBSP3.DX
P14,
W21
U13,
P16
MCBSP2.CLKR
V7
T5
McBSP2 receive clock. Serial shift clock reference for the receiver. CLKR is only
present on McBSP2.
I/O/Z
MCBSP2.FSR
W6
P6
McBSP2 receive frame sync. Frame synchronization for the receiver. FSR is only
present on McBSP2.
I/O/Z
MCBSP1.DR
H20
G16
McBSP receive data. Serial receive data input. DR is present on all McBSPs.
I
MCBSP2.DR
P10,
AA5
R6,
R5
MCBSP3.DR
AA17,
U18
R12,
P17
Camera Interface
CAM.EXCLK
H19
G13
Camera interface external clock. Output clock used to provide a timing reference
to a camera sensor.
O
CAM.LCLK
J15
H15
Camera interface line clock. Input clock to provide external timing reference from
camera sensor logic.
I
CAM.VS
L18
J17
Camera interface vertical sync. Vertical synchronization input from external
camera sensor.
I
CAM.HS
L15
K15
Camera interface horizontal sync. Horizontal synchronization input from external
camera sensor.
I
CAM.D[7:0]
J18,
J19,
J14,
K18,
K19,
K15,
K14,
L19
G14,
G12,
H16,
J15,
G17,
H17,
H14,
J16
Camera interface data. Data input bus to receive image data from an external
camera sensor.
I
CAM.RSTZ
M19
J14
Camera interface reset. Reset output used to reset or Initialize external camera
sensor logic.
O
ETM9 Trace Macro Interface
ETM.CLK
J15
H15
ETM9 Trace Clock. Clock output for standard ETM9 test/debug equipment.
O
ETM.SYNC
H19
G13
ETM9 Trace Synchronization. Trace Sync output for standard ETM9 test/debug
equipment.
O
ETM.D[7:0]
J18,
J19,
J14,
K18,
K19,
K15,
K14,
L19
G14,
G12,
H16,
J15,
G17,
H17,
H14,
J16
ETM9 Trace Packet data. Trace Packet outputs for standard ETM9 test/debug
equipment.
O
I = Input, O = Output, Z = High-Impedance
All core voltage supplies should be tied to the same voltage level (within 0.3 V). During system prototyping phases, it may be useful to maintain
a capability for independent measurement of core supply currents to facilitate power optimization experiments.
§See Sections 5.6.1 and 5.6.2 for special VSS considerations with oscillator circuits.
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