參數(shù)資料
型號: OMAP5910(RISC)
英文描述: Dual-Core Processor
中文描述: 雙核處理器
文件頁數(shù): 60/160頁
文件大?。?/td> 1997K
代理商: OMAP5910(RISC)
Functional Overview
48
August 2002 Revised August 2003
SPRS197B
3.6.12
LED Pulse Generator
There are two separate LED Pulse Generator (LPG) modules. Each LPG module provides an output for an
indication LED. The blinking period is programmable between 152 ms and 4 s or the LED can be switched
on or off permanently.
3.6.13
Real-Time Clock
The Real-Time Clock (RTC) module provides an embedded RTC for use in applications which need to track
real time. This peripheral is not an ultra-low-power module—meaning that the RTC module cannot be powered
independently without powering the OMAP5910 MPU core. Therefore, if an ultra-low-power RTC is desired
for a system application, an external RTC should be used.
The RTC module has the following features:
Time information (seconds/minutes/hours) directly in BCD code
Calendar information (day/month/year/day of the week) directly in BCD code up to year 2099
Interrupts generation, periodically (1s/1m/1h/1d period) or at a precise time of the day (alarm function)
30-s time correction
Oscillator frequency calibration
3.6.14
Frame Adjustment Counter
The frame adjustment counter (FAC) is a simple peripheral that counts the number of rising edges of one signal
(start of frame interrupt of the USB Function) during a programmable number of rising edges of a second signal
(transmit frame synchronization of McBSP2). The FAC may only be used with these specific USB Function
and McBSP2 signals. The count value can be used by system-level software to adjust the duration of the two
time domains with respect to each other to reduce overflow and underflow. If the data being transferred is audio
data, this module can be part of a solution that reduces pops and clicks. The FAC module generates one
second-level interrupt to the MPU.
3.7
DSP Public Peripherals
Peripherals on the DSP Public Peripheral bus are directly accessible by the DSP and DSP DMA. These
peripherals may also be accessed by the MPU and System DMA Controller via the MPUI interface. The MPUI
interface must be properly configured to allow this access.
3.7.1 Multichannel Buffered Serial Port (McBSP)
The Multichannel Buffered Serial Port (McBSP) provides a high-speed, full-duplex serial port that allow direct
interface to audio codecs and various other system devices. Refer to Section 3.6.3 for a list of features
provided by the McBSP. The DSP public peripheral bus has access to two McBSPs: McBSP1 and McBSP3.
NOTE:
All of the standard McBSP pins are not necessarily available on every McBSP on the OMAP5910
device. In the case of the two DSP McBSPs, the following pins are available:
McBSP1 pins:
CLKX (transmit clock)
FSX (transmit frame sync)
DX and DR (transmit and receive data)
CLKS (external reference to Sample Rate Generator)
McBSP3 pins:
CLKX (transmit clock)
FSX (transmit frame sync)
DX and DR (transmit and receive data)
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