參數(shù)資料
型號： OMAP5910(RISC)
英文描述： Dual-Core Processor
中文描述： 雙核處理器
文件頁數(shù)： 140/160頁
文件大小： 1997K
代理商： OMAP5910(RISC)
Electrical Specifications
128
August 2002 Revised August 2003
SPRS197B
5.9.2 McBSP as SPI Master or Slave Timing
Table 516 to Table 523 assume testing over recommended operating conditions (see Figure 520 through
Figure 523).
Table 516. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M30
tsu(DRV-CKXL)
th(CKXL-DRV)
Setup time, MCBSPx.DR valid before MCBSPx.CLKX low
15
2 6P
ns
M31
Hold time, MCBSPx.DR valid after MCBSPx.CLKX low
2
6 + 6P
ns
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX high
McBSP1
21
M32
tsu(BFXL-CKXH)
McBSP2
5
ns
McBSP3
10
M33
tc(CKX)
Cycle time, MCBSPx.CLKX
2P
16P
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
Table 517. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO.
PARAMETER
MASTER§
SLAVE
UNIT
MIN
MAX
MIN
MAX
M24
th(CKXL-FXL)
td(FXL-CKXH)
td(CKXH-DXV)
td(FXL-DXV)
Hold time, MCBSPx.FSX low after MCBSPx.CLKX low
Delay time, MCBSPx.FSX low to MCBSPx.CLKX high#
0.45T
0.55T
ns
M25
0.45C
0.55C
ns
M26
Delay time, MCBSPx.CLKX high to MCBSPx.DX valid
1
7
3P + 2
5P+ 18
ns
M29
Delay time, MCBSPx.FSX low to MCBSPx.DX valid
4P + 18
ns
For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.
P = 1/(Base frequency) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in ns for McBSP 2. Base frequency is 12 or 13 MHz.
§T =
CLKX period = (1 + CLKGDV) * P
C =
CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#MCBSPx.FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (MCBSPx.CLKX).
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M30
M26
M31
M24
M29
M25
LSB
MSB
M32
M33
Figure 520. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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