參數資料
型號: MC145574
廠商: Motorola, Inc.
英文描述: ISDN S/T-Interface Transceiver
中文描述: 綜合業(yè)務數字網S / T的接口收發(fā)器
文件頁數: 94/164頁
文件大?。?/td> 1072K
代理商: MC145574
MC145574
10–4
MOTOROLA
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR6
TSA B1
Enable
TSA B2
Enable
TSA D
Channel
Enable
Dout
Open Drain
GCI
Indirect
Mode
Enable
CLK1
CLK0
OR6(7) — Control Register, TSA B1 Enable
This bit is used to enable the B1 channel in IDL2 timeslot mode. The B1 timeslot is defined through
the OR0 and OR3 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all
channels enter timeslot mode. If in timeslot mode and TSA B1 enable is a 0, then the B1 channel
is not present on Dout, and the transmit data on the S/T interface is forced to all 1s and Dout is high
impedance.
OR6(6) — Control Register, TSA B2 Enable
This bit is used to enable the B2 channel in IDL2 timeslot mode. The B2 timeslot is defined through
OR1 and OR4 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all chan-
nels enter timeslot mode. If in timeslot mode and TSA B2 enable is a 0, then the B2 channel is not
present on Dout, and the transmit data on the S/T interface is forced to all 1s and Dout is high impedance.
OR6(5) — Control Register, TSA D Channel Enable
This bit is used to enable the D channel in IDL2 timeslot mode. The D timeslot is defined through
the OR2 and OR5 registers. Whenever any channel (B1, B2, or D) is enabled for timeslot mode, all
channels enter timeslot mode. If in timeslot mode and TSA D enable is a 0, then the D channel is
not present on Dout, and the transmit data on the S/T interface is forced to all 1s and Dout is high
impedance.
OR6(3) — Control Register, Dout Open Drain
When operating in NT Terminal mode, this bit configures the Dout pin as an open drain when set to
a 1. When this bit is set to a 0, the Dout pin goes high impedance between B and D channels.
OR6(2) — Control Register, GCI Indirect Mode Enable
When the device is initialized, this bit is a logic 0, the inactive state; i.e., normal IDL2 mode. When
set to a logic 1, the IDL2 port is reconfigured to behave like a GCI frame. This is called GCI indirect
mode. When GCI indirect mode has been enabled, the GCI timeslot can be selected through the S(2:0)
bits in OR5.
OR6(1:0) — Control Register, CLK(1:0)
In GCI indirect mode, these two bits control the output clock frequency of GCI DCL. CLK(1:0)=0H
is the initialized state.
Table 10–4. S(2:0) GCI Timeslot
Assignment
CLK1
CLK0
GCI DCL
0
0
2.048 MHz
0
1
2.048 MHz
1
0
1.536 MHz
1
1
512 kHz
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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