參數(shù)資料
型號(hào)： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 40/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
5–2
MOTOROLA
back high after the transaction, before another rising edge of SCPCLK is encountered. Note that
SCP Rx is ignored during the time that SCP Tx is being driven. Also note that SCP Tx comes out
of high impedance only when it is transmitting data.
Figure 5–1. Serial Control Port Nibble Register Read Operation
SCPCLK
R/W
A1
A2
A0
D3
D2
D0
D1
HIGH IMPEDANCE
DONT CARE
DONT CARE
SCP Rx
SCP Tx
SCPEN
A nibble register write is an 8–bit SCP transaction. Figure 5–2 illustrates this process. To initiate an
SCP nibble register write, the SCPEN pin must be brought low. Following this, an R/W bit followed
by three primary address bits are shifted (MSB first) into an intermediate buffer register on the first
four rising edges of SCPCLK following the high–to–low transition of SCPEN. If a write operation is
to be performed, then R/W should be a 0. The three address bits, clocked in after the R/W bit, select
the nibble register to be written to. The data shifted in on the next four rising edges of SCPCLK is
then written to the selected register. Throughout this whole operation the SCP Tx pin remains in high–
impedance state. Note that if a selected register or bit in a selected register is “read only”, then a
write operation has no effect.
Figure 5–2. Serial Control Port Nibble Register Write Operation
SCPEN
R/W
A1
A2
A0
D3
D2
D0
D1
HIGH IMPEDANCE
DONT CARE
SCPCLK
SCP Tx
SCP Rx
DONT CARE
NOTES:
1. R/W = 0 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.
4. A2, A1, A0 = 0 to 6.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC145574AEG 制造商:Freescale Semiconductor 功能描述:
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