參數(shù)資料
型號： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 75/164頁
文件大小： 1072K
代理商： MC145574
MC145574
8–7
MOTOROLA
This function may be used in multidrop configurations or in applications where the output B channel
transmission must be held in the “idle 1s” condition. Note that NR5(3) is a read/write bit in the TE
mode.
NR5(2)
NT: Idle B2 Channel
— In the NT mode, NR5(2) functions as a B2 channel idle bit. When NR5(2)
is 0, the MC145574 functions normally, where data received in the B2 channel timeslot via the IDL2
is modulated onto the S/T transmission loop in the B2 channel timeslot. When NR5(2) is 1, data input
on the IDL2 Rx pin in the B2 channel timeslot is ignored, and the “idle 1s” condition exists on the
B2 channel timeslot on the S/T transmission loop. Note that the default condition (i.e., after power–up
or after a reset) for NR5(2) is 0, thereby allowing the data received via the IDL2 interface to be modu-
lated onto the transmission loop. Note that NR5(2) is a read/write bit in the NT mode.
TE: Enable B2 Channel
— In the TE mode of operation, NR5(2) functions as a B2 channel enable
bit. In the TE mode B2 channel data is forced to the “idle 1s” condition on the S/T transmission loop
when NR5(2) is 0. When NR5(2) is 1 (enabled), B2 channel data input via the IDL2 interface is modu-
lated and transmitted onto the S/T transmission loop in the B2 channel timeslot. The default condition
(i.e., after power–up or after a reset) for TE mode devices forces the B2 channel bits to the “idle 1s”
condition. This is to avoid B channel interference until the B channels are assigned by the network.
This function may be used in multidrop configurations or in applications where the output B channel
transmission must be held in the “idle 1s” condition. Note that NR5(2) is a read/write bit in the TE
mode.
NR5(1) — Invert B1 Channel
When NR5(1) is 0, the B1 channel data received via the IDL2 interface is transmitted normally on
the transmission loop. When NR5(1) is set to 1, the B1 channel data received via the IDL2 interface
is inverted before entering the modulator portion of the MC145574 S/T transceiver, prior to transmission
on the S/T loop in the B1 timeslot. The selected B1 channel data received via the transmission loop
is also inverted before being output on the IDL2 Tx pin when this function is invoked. This feature
is useful in applications where it is required to use inverted data. Note that NR5(1) is a read/write
bit.
NR5(0) — Invert B2 Channel
When NR5(0) is 0, the B2 channel data received via the IDL2 interface is transmitted normally on
the transmission loop. When NR5(0) is set, the B2 channel data received via the IDL2 interface is
inverted before entering the modulator portion of the MC145574 S/T transceiver prior to transmission
on the S/T loop in the B2 timeslot. The selected B2 channel data received via the transmission loop
is also inverted before being output on the IDL2 Tx pin when this function is invoked. This feature
is useful in applications where inverted data is required. Note that NR5(0) is a read/write bit.
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 6 (NR6) is as follows.
b3
b2
b1
b0
NR6
2B+D IDL2 Loopback
Swap B1 and B2
rw
rw
NR6(3) – 2B+D IDL2 Loopback
When NR6(3) is 0, the MC145574 S/T transceiver functions normally. When NR6(3) is set to 1, the
B1, B2, and D channel data input on the IDL2 Rx input pin are buffered and returned to the IDL2
Tx output pin on the next IDL2 cycle. The output B1, B2, and D channel data is passed unchanged
to the modulator portion of the transceiver and transmitted onto the S/T loop (i.e., the loopback is
transparent). Note that NR6(3) is a read/write bit.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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PDF描述
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