參數(shù)資料
型號(hào): MC145574
廠商: Motorola, Inc.
英文描述: ISDN S/T-Interface Transceiver
中文描述: 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù): 92/164頁
文件大小: 1072K
代理商: MC145574
MC145574
10–2
MOTOROLA
Table 10–2. Overlay Register Initialization After Any Reset
IDL TE
IDL NT
GCI TE
GCI NT
OR0
00
00
00
00
OR1
04
04
00
00
OR2
08
08
00
00
OR3
00
00
00
00
OR4
04
04
00
00
OR5
08
08
00
00
OR6
00
00
00
00
OR7
00
00
00
00
OR8
00
00
00
01
OR15
00XX XXXX
00XX XXXX
00XX XXXX
00XX XXXX
NOTES:
1. All values in hexadecimal unless shown otherwise.
2. BR15 and OR15 are the same register.
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR0
Din B1 Channel Timeslot Bits (7:0)
OR0(7:0) — Tx B1 Channel Timeslot
This register allows the B1 channel timeslot input to the Din pin to be allocated 1 of 256 start points,
corresponding to each 2–bit boundary defined by the CLK. The timeslot can be either 8 or 10 CLKs
wide. The default value for OR0 is 00H.
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR1
Din B2 Channel Timeslot Bits (7:0)
OR1(7:0) — Tx B2 Channel Timeslot
This register allows the B2 channel timeslot input to the Din pin to be allocated 1 of 256 start points,
corresponding to each 2–bit boundary defined by the CLK. The timeslot can be either 8 or 10 CLKs
wide. The default value for OR1 is 04H.
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR2
Din D Channel Timeslot Bits (7:0)
OR2(7:0) — Tx D Channel Timeslot
This register allows the D channel timeslot input to the Din pin to be allocated 1 of 256 start points,
corresponding to each 2–bit boundary defined by the CLK. The default value for OR2 is 08H.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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