參數(shù)資料
型號: MC145574
廠商: Motorola, Inc.
英文描述: ISDN S/T-Interface Transceiver
中文描述: 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù): 50/164頁
文件大?。?/td> 1072K
代理商: MC145574
MC145574
6–4
MOTOROLA
When control of the SCP interface is available, a pseudo GCI mode can be activated through the
GCI control register. In the indirect mode, the SCP interface operates as normal and the IDL2 interface
operates in a GCI type 2B+D data format mode. This means that the 2B+D data is assembled in a
pseudo GCI frame for transmission, but the C/I, monitor, and A/E fields are high impedance. For recep-
tion, data is recognized in the B and D channels but is ignored in the C/I, M, and A/E channels. The
SCP interface is available as normal.
Figure 6–2. GCI Indirect Mode
FSC
DCL
Dout
Din
B2
D D
BASIC GCI CHANNEL IN INDIRECT MODE
FSC = 8 kHz
DCL = 512 kHz
Dout/Din = 256 kbps
125
μ
s
B1
B2
D D
B1
The following GCI control bits are located in the overlay register set, in OR5 and OR6.
GCI_IND EN, OR6(b2)
At reset, this bit is set to a logic zero; the inactive state (i.e., normal IDL2 mode). When set to a logic
one, the IDL2 port is reconfigured to have the same 2B+D data format as a GCI interface. When GCI
indirect mode is inactive, OR5(2:0) and OR6(1:0) bits are disabled.
CLK(1:0), OR6(b1, b0)
In master mode, these two bits control the output clock frequency of GCI_DCL. CLK(1:0)=0 is the
default state.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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