參數(shù)資料
型號： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 77/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
9–1
MOTOROLA
There are 16 byte registers (BR0 through BR15) in the MC145574. Control, status, and maintenance
information reside in these byte registers, which are accessed via the SCP. For a detailed description
of access procedures, refer to Section 5. The nomenclature used in this data sheet is such that BR2(3)
refers to byte register 2, bit 3.
The byte register map is fully compatible with the byte register map of the MC145474, with the exception
of:
1. The functions that were related to the IDL2 A/M FIFOs have been removed. Writing to these registers
has no effect, and reading them returns FFH.
2. The TTL input level bit BR13(6) has been removed. The digital inputs are CMOS and TTL compatible.
Writing to this bit has no effect, and reading it returns 0 or 1 depending on what value, if any, has been
written.
3. The only addition to the byte register map is the bit BR15(0), used for enabling the overlay registers.
Table 9–1. Byte Register Map for NT Mode of Operation
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR2
SC1.1
SC1.2
SC1.3
SC1.4
BR3
Q.1
Q.2
Q.3
Q.4
Q Qual
Interrupt
Every
Multiframe
BR4
FV7
FV6
FV5
FV4
FV3
FV2
FV1
FV0
BR5
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
BR6
B1 S/T
Loopback
Transparent
B1 S/T
Loopback
Non–
Transparent
B2 S/T
Loopback
Transparent
B2 S/T
Loopback
Non–
Transparent
IDL2 B1
Loopback
Transparent
IDL2 B1
Loopback
Non–
Transparent
IDL2 B2
Loopback
Transparent
IDL2 B2
Loopback
Non–
Transparent
BR7
Activation
Procedures
Disabled
Active Only
NT Enable
Enable
Multiframing
Invert E
Channel
IDL2 Master
Mode
IDL2 Clock
Speed (LSB)
LAPD
Polarity
Control
Activation
Timer #2
Expired
BR9
TXSC2.1
TXSC2.2
TXSC2.3
TXSC2.4
TXSC3.1
TXSC3.2
TXSC3.3
TXSC3.4
BR10
TXSC4.1
TXSC4.2
TXSC4.3
TXSC4.4
TXSC5.1
TXSC5.2
TXSC5.3
TXSC5.4
BR11
Do Not React
to INFO 1
Do Not React
to INFO 3
Rx INFO
State B1
Rx INFO
State B0
Tx INFO
State B1
Tx INFO
State B0
External S/T
Loopback
Transmit
96 kHz
Test Signal
BR12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BR13
NT1 Star
Mode
Reserved
IDL2 Clock
Speed (MSB)
Mute B2
on IDL2 Tx
Mute B1
on IDL2 Tx
Force Echo
Channel
to Zero
Not
Applicable
Reserved
BR14
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BR15
Overlay
Register
Enabled
Rev 5
Rev 4
Rev 3
Rev 2
Rev 1
Rev 0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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