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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁(yè)數(shù)： | 23/164頁(yè) |
| 文件大小： | 1072K |
| 代理商： | MC145574 |
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MC145574
3–1
MOTOROLA
CCITT I.430, ETSI ETS 300012, and ANSI T1.605 define five information states for the S/T transceiver.
When the NT is in the fully operational state, it transmits INFO 4. When the TE is in the fully operational
state, it transmits INFO 3. INFO 1 is transmitted by the TE when it wants to wake up the NT. INFO 2
is transmitted by the NT when it wants to wake up the TE, or in response to the TE’s transmitted
INFO 1. These states cause unique patterns of symbols to be transmitted over the S/T–interface.
Only when the S/T loop is in the fully activated state are the 2B+D channels of data transmitted over
the interface.
When configured as an NT, an S/T transceiver can be in any of the following transmission states shown
in Table 3–1.
Table 3–1. NT Mode Transmission States
Information State
Description
INFO 0
The NT transmits 1s in every bit position. This corresponds to no signal being transmitted.
INFO 2
The NT sets its B1, B2, D, and E channels to 0. The A bit is set to 0. (See Sections 3.12.1 and
3.12.2.)
INFO 4
INFO 4 corresponds to frames containing operational data on the B1, B2, D, and E channels.
The A bit is set to 1.
When configured as a TE, an S/T transceiver can be in any of the following transmission states shown
in Table 3–2.
Table 3–2. TE Mode Transmission States
Information State
Description
INFO 0
The TE transmits 1s in every bit position. This corresponds to no signal being transmitted.
INFO 1
The TE transmits a continuous signal with the following pattern: positive 0, negative 0, six 1s.
This signal is asynchronous to the NT.
INFO 3
INFO 3 corresponds to frames containing operational data on the B1, B2, and D channels. If
INFO 4 or INFO 2 is being received, INFO 3 will be synchronized to it.
The NT activates the loop by transmitting INFO 2 to the TE(s). This is accomplished in the MC145574
by setting NR2(3) to a 1 (see Section 3.12.3). Note that this bit is internally reset to 0 after the internal
activation state machine has recognized its active transition.
The TE on receiving INFO 2 synchronizes to it and transmits back INFO 3 to the NT. The NT, on
receiving INFO 3 from the TE, responds with INFO 4, thus activating the loop.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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