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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁(yè)數(shù)： | 101/164頁(yè) |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
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MC145574
11–3
MOTOROLA
!
The MC145574 in the TE mode of operation generates an interrupt every time a collision occurs on
the D channel. CCITT I.430, ETSI ETS 300012, and ANSI T1.605 define a collision as having occurred
when the demodulated E bit from the NT does not match the previously modulated D bit from the
TE. Since the NT reflects back its received D data in the E echo channel, the TE knows that a collision
occurring indicates that another TE has gained access to the D channel. When a collision occurs
NR3(1) gets set. If the corresponding interrupt enable bit (NR4(1)) is set high, then IRQ goes low.
The D channel collision interrupt is cleared by writing a 0 to NR3(1).
When configured as an NT, the MC145574 has automatic access to the D channel. This is because
the S/T–interface is designed for communication between a single NT and one or more TEs. As such,
the NT does not have to compete for access to the D channel. Thus, there are no DREQUEST or
DGRANT functions associated with the NT mode of operation.
Data present in the D bit positions of the IDL2 frame on IDL2 Rx are modulated onto the D bit timeslots
on the S/T loop. Demodulated D channel data from the TE(s) is transmitted onto IDL2 Tx in accordance
with the IDL2 specification.
The ECHO function of an NT–configured S/T transceiver is performed internally in the MC145574.
To assist in testing an S/T loop, the MC145574 features the SCP test bits BR7(4) and BR13(2). Setting
BR7(4) in the NT mode inverts the E echo channel (i.e., the logical inverse of the demodulated D chan-
nel data from the TE(s) is transmitted in the E channel). Setting BR13(2) to a 1 forces the E channel
to all 0s. Refer to Section 9 for a more detailed description of these test bits. Setting BR13(7) to a
1 puts the NT–configured MC145574 S/T transceiver into the NT1 Star mode of operation. In this
mode, the bits to be ECHOed back to the TE(s) are obtained from the ECHO IN pin. Refer to Section 13
for a more detailed description of this function.
The active polarity of the DREQUEST and DGRANT signals may be reversed by setting the LAPD
polarity control bit (BR7(1)) in the SCP. When BR7(1) is a 0, the active polarity is as described above.
Conversely, when BR7(1) is a 1, the MC145574 will drive DGRANT to a logic 0 when DGRANT is
active, and to a logic 1 when DGRANT is inactive. Also, when BR7(1) is 1, DREQUEST will be consid-
ered to be active low.
In GCI indirect mode, the D channel operation is identical to that of the IDL2.
In GCI direct mode, the DREQUEST/DGRANT/CLASS pins are replaced by C/I commands. D channel
availability is indicated by two methods using the SG nomenclature; SG meaning stop/go. The stop/go
refers to the availability of the D channel on the S/T loop. (1 = Stop and 0 = Go.)
The stop/go signal is available in two forms. In SCIT terminal mode, the stop/go bit is output by the
device in CH2 bit 4 of the C/I channel. This method is compatible with the IOM–2 terminal mode and
is also compatible with the MC68302. This mode must be enabled by selecting GCI_M(2:0) = 4H (termi-
nal mode) and writing to OR7(6) (S/G bit enable).
The stop/go signal is also available as a pin, SG, as an alternative to the SCIT terminal method.
The SCIT terminal frame structure for the T2 device is as follows.
The remaining CH1 and CH2 channels are for use by other devices in the terminal application,
and do not form part of this specification.
The class of message is selected using the C/I commands AR8 and AR10.
AREOM can be used to terminate the D channel message.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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