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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁(yè)數(shù)： | 44/164頁(yè) |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
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MC145574
5–6
MOTOROLA
There are five signals which constitute the SCP bus.
1.
SCP Tx
2.
SCP Rx
3.
SCPCLK
4.
SCPEN
5.
IRQ
A description of each signal follows.
SCP Tx is used to output control, status, and data information from the MC145574 S/T transceiver.
The data is output in either 4–bit nibble or 8–bit byte groupings. The data is output in 4–bit nibble
groupings during a nibble register read and in 8–bit byte groupings during a byte register read. Data
is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
In a nibble register read transaction, the fourth rising edge of SCPCLK after SCPEN goes low shifts
the LSB of the 3–bit nibble address into the MC145574. The following falling edge of SCPCLK shifts
out the first bit of the selected nibble register (MSB) and takes SCP Tx out of the high–impedance
state. The next three falling edges of SCPCLK shift out the other three bits of the selected nibble
register. When the last bit (LSB) has been shifted out, SCPEN should be returned high. This action
returns SCP Tx to a high–impedance state.
In a byte register read transaction, the eighth rising edge of SCPCLK after SCPEN goes low shifts
in the LSB of the 4–bit byte address. The following falling edge of SCPCLK (provided SCPEN is still
low) shifts out the first bit (MSB) of the selected byte register and takes SCP Tx out of high impedance.
The next seven falling edges of SCPCLK shift out the remaining seven bits of the selected byte register.
When the last bit (LSB) has been shifted out, SCPEN should be returned high. This action returns
SCP Tx to a high–impedance state.
SCP Rx is used to input control, status, and data information to the S/T transceiver. Data is shifted
into the device on rising edges of SCPCLK. The format for the input of data is as follows: the first
bit is the R/W bit (1 = read, 0 = write). This bit selects the operation to be performed on the selected
registers within the MC145574 S/T transceiver. The next three bits address one of eight specific nibble
registers within the MC145574 S/T transceiver on which the read or write operation is to be performed.
The address bits are shifted in MSB first. The last four bits are either the data bits (MSB first) that
are to be written to the S/T transceiver nibble register (NR0 through NR6), or are four additional address
bits (if NR7 had been addressed). These address bits select one of the 16–byte–wide registers (which
are accessed during the next eight cycles of the SCPCLK or a second 8–bit access). SCP Rx is ignored
when data is being shifted out on SCP Tx, or when SCPEN is high.
This is an input to the device used for controlling the rate of transfer of data into and out of the SCP.
Data is shifted into the part from SCP Rx on rising edges of SCPCLK. Data is shifted out of the part
on SCP Tx on falling edges of SCPCLK. SCPCLK can be any frequency up to 4.096 MHz.
An SCP transaction takes place when SCPEN is brought low. Note that SCPCLK is ignored when
SCPEN is high; i.e., it may be continuous or it can operate in the burst mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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