參數(shù)資料
型號： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 70/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
8–2
MOTOROLA
Table 8–3. Nibble Register Initialization After Any Reset
IDL TE
IDL NT
GCI TE
GCI NT
NR0
0
0
0
0
NR1
0
0
0
0
NR2
0
0
0
0
NR3
8
0
8
0
NR4
0
0
0
0
NR5
0
0
0
0
NR6
0
0
0
0
NOTE: All values in hexadecimal unless shown otherwise.
This register is a read/write register and can be reset by a hardware reset. A per–bit description of
nibble register 0 (NR0) follows.
b3
b2
b1
b0
NR0
Software Reset
Transmit Power–Down
Absolute Minimum
Power
Return to Normal
rw
rw
rw
rw
NR0(3) — Software Reset
When NR0(3) is 0, the MC145574 functions normally. When this bit is set to 1, a software reset is
applied to the internal circuits of the S/T transceiver. The effect of the software reset is the equivalent
of holding the external reset input low (hardware reset), except that NR0(3:0) is not reset. Thus, when
this bit is set, all internal registers (except NR0) are returned to their initial state. Application of either
a hardware or software reset has the effect of re–initializing all the internal registers; it does not prevent
access to the SCP. Note that NR0(3) is a read/write bit.
NR0(2) — Transmit Power–Down
When NR0(2) is 0, the S/T transceiver functions normally. When NR0(2) is set to 1, the S/T transceiver
enters a power conservation mode. In this mode the transmit section of the transceiver is held in the
INFO 0 state and IDL2 Tx is held in the “idle 1s” condition. When NR0(2) = 1, the receive circuitry
of the transceiver is still functional, allowing an interrupt to be generated in the event of a change
in state of the received signal. Note that NR0(2) is a read/write bit. This bit has no effect on the operation
of the SCP. If BR13(1) is set, the S/T transceiver outputs data on Dout.
NR0(1) — Absolute Minimum Power
When this bit is 0, the MC145574 functions normally. When this bit is set to 1, the chip enters a power
conservation mode. In this mode a software reset is applied to the chip, all circuits are initialized, all
clocking of the device is blocked, and the nonessential bias to the analog functions of the transceiver
are removed such that the device consumes the absolute minimum amount of power. The transmit
section of the chip is held in the INFO 0 state and IDL2 Tx is held in the “idle 1s” condition. Note
that NR0(1) is a read/write bit. This bit has no effect on the operation of the SCP. In this mode, only
the SCP can operate.
NR0(0) — Return to Normal
When this bit is 0, the MC145574 functions normally. When this bit is 1, the following bits are reset:
BR11(0) 96 kHz Test Signal
BR11(1) External S/T Loopback
BR6(7:0)
Note that NR0(0) is a read/write bit.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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