參數(shù)資料
型號： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 81/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
9–5
MOTOROLA
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR5
BPV7
BPV6
BPV5
BPV4
BPV3
BPV2
BPV1
BPV0
BR5(7:0) is the output of an 8–bit binary counter. This counter counts the number of unbalanced frames.
A frame in which the total number of positive pulses is different from the total number of negative
pulses constitutes an unbalanced frame. BR5(7:0) is applicable to both NT and TE modes of operation.
It is a read/write register, thereby allowing the user to program the counter to a predetermined value.
The counter is initialized to “100” by a hardware/software reset. Note that the counter, upon reaching
a value of “FF”, will not roll over; i.e., it will remain at “FF” until the user rewrites a starting value.
Note that BR5(7) is the MSB of the counter and BR5(0) is the LSB.
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR6
B1 S/T
Loopback
Transparent
B1 S/T
Loopback
Non–
Transparent
B2 S/T
Loopback
Transparent
B2 S/T
Loopback
Non–
Transparent
IDL2 B1
Loopback
Transparent
IDL2 B1
Loopback
Non–
Transparent
IDL2 B2
Loopback
Transparent
IDL2 B2
Loopback
Non–
Transparent
BR6(7) — B1 S/T Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the device enters a “B1 S/T Loopback Transparent
Mode”. In this mode, data entering the device from RxP/PxN in the B1 timeslot is demodulated and
remodulated back out on TxP/TxN in the B1 timeslot. The demodulated B1 data continues to present
itself on IDL2 Tx in the B1 timeslot (hence, the term “transparent”). Data entering the part from IDL2
Rx in the B1 timeslot is ignored. This bit is reset to 0 by either a software reset, a hardware reset,
or in the “return to normal” mode (NR0(0) = 1).
BR6(6) — B1 S/T Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0 the device functions normally. When this bit is 1, the device enters a “B1 S/T Loopback Non–Trans-
parent Mode”. In this mode, data entering the device from RxP/RxN in the B1 timeslot is demodulated
and remodulated back out on TxP/TxN in the B1 timeslot. Data entering the part from IDL2 Rx in
the B1 timeslot is ignored. IDL2 Tx ignores the demodulated B1 data, presenting in its stead the “idle
1s” condition in the IDL2 Rx B1 timeslot (hence, the term “non–transparent”). This bit is reset to 0
by either a software reset, a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(5) — B2 S/T Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the device enters a “B2 S/T Loopback Transparent
Mode”. In this mode, data entering the device from RxP/RxN in the B2 timeslot is demodulated and
remodulated back out on TxP/TxN in the B2 timeslot. The demodulated B2 data continues to present
itself on IDL2 Tx in the B2 timeslot (hence, the term “transparent”). Data entering the part from IDL2
Rx in the B2 timeslot is ignored. This bit is reset to 0 by either a software reset, a hardware reset,
or in the “return to normal” mode (NR0(0) = 1).
BR6(4) — B2 S/T Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the device enters a “B2 S/T Loopback Non–Trans-
parent Mode”. In this mode, data entering the device from RxP/RxN in the B2 timeslot is demodulated
and remodulated back out of TxP/TxN in the B2 timeslot. Data entering the part from IDL2 Rx in the
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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MC145574AEG 制造商:Freescale Semiconductor 功能描述:
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