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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁(yè)數(shù)： | 83/164頁(yè) |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
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MC145574
9–7
MOTOROLA
Note that if activation procedures are disabled as a TE, causing INFO 3 to be transmitted, then this
state may or may not be commensurate with receiving INFO 0 from the NT. In the event that INFO 0
is being received, the transmitted INFO 3 is transmitted asynchronously. If either INFO 2 or INFO 4
are subsequently received, then the TE’s INFO 3 aligns itself to the received signal in accordance
with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. Note also that a TE wakes up if it receives
either INFO 2 or INFO 4 from the NT. However, an NT transmitting INFO 0 will not wake up to the
reception of INFO 3 from the TE. For an NT to be woken up by a TE, it must first receive INFO 1
from the TE and then proceed to go through the subsequent handshaking. BR7(7) is reset to 0 by
application of either a hardware or software reset.
BR7(6) — NT: Active Only NT Enable
TE: D Channel Procedures Ignored
When the MC145574 is configured as a TE, this bit is used to enable/disable D channel contention
procedures in accordance with the CCITT I.430, ETSI ETS 300012, and ANSI T1.605. When this
bit is 0, the D channel procedures are adhered to as per the DREQUEST, DGRANT, and CLASS pin
descriptions. When this bit is 1, the D channel procedures are ignored, allowing the data present in
the D channel on IDL2 Rx to be modulated regardless of the status of DREQUEST and DGRANT.
BR7(6) = 1 causes the TE to disregard the demodulated E echo bits. The TE’s D data will be modulated
regardless. This bit is a read/write bit and is reset to 0 by application of either a software or a hardware
reset. When configured as an NT, this bit enables the “active only NT” mode. In this mode, the NT
is restricted to the G2 or G3 state; i.e., the device is either activated or attempting to activate. The
device is never allowed to fully deactivate.
BR7(5) — NT: Enable Multiframing
TE: Not Applicable
When the MC145574 is configured as an NT, this bit is used to enable/disable multiframing in accor-
dance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. When this bit is 0, multiframing is dis-
abled. In this mode the M, Fa, and S bauds transmitted from the NT will be binary 0. When this bit
is 1, multiframing is enabled. In this mode, the M, Fa, and S bauds will adhere to the multiframing
coding rules as outlined in CCITT I.430 and ANSI T1.605. Since the TE cannot initiate multiframing,
this bit has no application in this mode. This bit is a read/write bit and is reset to 0 by application
of either a software or a hardware reset.
BR7(4)
NT: Invert Echo Channel
— When the MC145574 is configured as an NT, this bit is used to determine
the polarity of the transmitted echo channel from the NT to the TE. When this bit is a 0, the transmitted
E bit is the same as the previously demodulated D bit from the TE(s). When this bit is 1, the transmitted
E bit is the logical inverse of the previously demodulated D bit. This bit is a read/write bit and is reset
to 0 by application of either a software or hardware reset.
TE: Map E Bits to IDL2
— With the MC145574 configured as a TE and this bit a 0, the TE outputs
the demodulated D channel data in the D timeslot on the IDL2 Tx. When this bit is set to 1, the TE
outputs the demodulated E channel in the D timeslot on IDL2 Tx, neglecting the demodulated D channel
data. This bit is a read/write bit and is reset to 0 by application of either a software or a hardware
reset.
BR7(3)
NT: IDL2 Master Mode
— With the MC145574 configured as an NT, this bit determines whether the
device operates in IDL2 slave or IDL2 master mode. When this bit is 0, the NT operates in the IDL2
slave mode, where IDL2 SYNC and IDL2 CLK are inputs to the device. When this bit is 1, the NT
operates in the NT IDL2 master mode, where IDL2 SYNC and IDL2 CLK are outputs from the device.
This bit is a read/write bit OR’d with the M/S pin and is reset to 0 by application of either a software
or hardware reset.
TE: IDL2 Free Run
— When the MC145574 is configured as a TE and the loop is active, the device
will output IDL2 SYNC and IDL2 CLK synchronous to the inbound data from the NT. When the loop
is inactive and this bit is 0, the TE does not output IDL2 SYNC or IDL2 CLK. If this bit is 1, the TE
outputs IDL2 SYNC and IDL2 CLK regardless of the status of the loop. If the loop is inactive, these
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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| MC145574AEG | 制造商:Freescale Semiconductor 功能描述: |
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