參數(shù)資料
型號(hào): MC145574
廠商: Motorola, Inc.
英文描述: ISDN S/T-Interface Transceiver
中文描述: 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁(yè)數(shù): 88/164頁(yè)
文件大?。?/td> 1072K
代理商: MC145574
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MC145574
9–12
MOTOROLA
BR11(0) — Transmit 96 kHz Test Signal
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the MC145574 functions normally. When this bit is 1, the device transmits a 96 kHz square wave
test signal on TxP/TxN. This test signal can be used for test purposes. This 96 kHz test signal qualifies
as a “Transmit INFO X” state. Correspondingly, the MC145574 receiving the 96 kHz test signal will
be in the “Receive INFO X” state. Application of a hardware or software reset will reset this bit to 0.
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR12
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte register 12 is reserved for Motorola use only.
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR13
NT: NT1
Star Mode
TE: Not
Applicable
Reserved
IDL2 Clock
Speed
(MSB)
Mute B2 on
IDL2 Tx
Mute B1 on
IDL2 Tx
NT: Force
Echo
Channel to
Zero
TE: Not
Applicable
NT: Not
Applicable
TE: Force
IDL2 Tx
Reserved
BR13(7) — NT: NT1 Star Mode
TE: Not Applicable
This bit is a read/write bit and is only applicable to the NT mode of operation. When this bit is 0, the
device functions normally. When this bit is 1, the device is configured for NT1 Star mode operation.
Refer to Section 11 for a detailed description of this mode. This bit is reset to 0 by application of either
a hardware or software reset.
BR13(6)
This bit has no function and is reserved for Motorola use only.
BR13(5) — IDL2 Clock Speed (MSB)
This bit is a read/write bit and is applicable to both NT and TE modes of operation. BR13(5), in conjunc-
tion with BR7(2), determines the IDL2 CLK frequency when operating in the IDL2 master mode. BR7(2)
is the LSB and BR13(5) is the MSB. The code corresponding to each IDL2 clock frequency is as shown
in the description for BR7(2). Application of either a hardware or a software reset will reset this bit
to 0. See Table 9–3.
BR13(4) — Mute B2 on IDL2
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the data transmitted on the B2 channel on IDL2
Tx will be forced to the “idle 1s” condition. This feature is primarily used in the NT1 Star mode operation.
Refer to Section 11 for a detailed description of this mode. Application of a hardware or software reset
resets this bit to 0.
BR13(3) — Mute B1 on IDL2
This bit is a read/write bit and is applicable to both NT and TE modes of operation. When this bit
is 0, the device functions normally. When this bit is 1, the data transmitted on the B1 channel on IDL2
Tx will be forced to the “idle 1s” condition. This feature is primarily used in the NT1 Star mode operation.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
MC14559BDWR2 Successive Approximation Registers
MC14559B Successive Approximation Registers
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