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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁(yè)數(shù)： | 27/164頁(yè) |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
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MC145574
4–1
MOTOROLA
The Interchip Digital Link (IDL2) of the MC145574 is backwards compatible with the IDL of the
MC145474/75 S/T transceiver of first generation. In addition to the standard operating mode, this en-
hanced interface features new modes that are programmable through the SCP.
The IDL2 is a four–wire interface used for full–duplex communication between ICs on the board level.
The interface consists of a transmit path, a receive path, an associated clock, and a sync signal. These
signals are known as Dout, Din, DCL, and FSC, respectively. The clock determines the rate of exchange
of data in both the transmit and receive directions, and the sync signal controls when this exchange
is to take place. Three channels of data are exchanged every 8 kHz. These channels consist of two
64 kbps B channels and one 16 kbps D channel used for full–duplex communication between the
NT and TE.
There are two modes of operation for an IDL2 device: IDL2 master and IDL2 slave. If an IDL2 device
is configured as an IDL2 master, then FSC and DCL are outputs from the device. Conversely, if an
IDL2 device is configured as an IDL2 slave, then FSC and DCL are inputs to the device. Ordinarily
the MC145574 should be configured as an IDL2 slave when acting as an NT, and as an IDL2 master
when acting as a TE. The exception to this rule is the option to configure the NT as an IDL2 master.
The TE configured MC145574 also features the new option of operating in the IDL2 slave mode. These
operation modes are described in Section 4.3.
There are six pins associated with the IDL2 interface.
FSC/FSR
This pin is normally FSC and is an input/output pin to which all serial interface events are synchronized.
This pin is periodic at 8 kHz. In the master mode, the pin is an output and is either derived from the
S/T frame or from the XTAL. In the slave mode, this pin is an input.
FSC can be reconfigured through the SCP to be FSR. In this mode, the IDL2 operates with two indepen-
dent frame syncs, one for the Tx direction (FST) and one for the Rx direction (FSR). FSR is bidirectional,
the direction depending on whether the IDL2 is a master or a slave. See Register OR7 description.
DCL
This is an input/output pin that provides the clock to the serial interface. In the master mode, this pin
is an output. In the slave mode, this pin is an input. The clock is continuous and the edges are synchro-
nous with the frame sync.
When DCL is an output, the clock rate can be programmed through the SCP to be 2.56 MHz,
2.048 MHz, 1.536 MHz, or 512 kHz. When DCL is an input, the clock rate can be between 512 kHz
and 4096 kHz (DCL should be a multiple of FSC.) Selection of the clock frequency is accomplished
in the same manner as used in MC145474, through the bits BR7(2) and BR13(5). See Table 4–1
for IDL2 clock speeds.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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相關(guān)PDF資料 |
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| MC14559BDWR2 | Successive Approximation Registers |
| MC14559B | Successive Approximation Registers |
| MC14559BCP | Successive Approximation Registers |
| MC1455 | Timing Circuit |
| MC1455BD | Timing Circuit |
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| MC145574AEG | 制造商:Freescale Semiconductor 功能描述: |
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