
MC145574
9–6
MOTOROLA
B2 timeslot is ignored. IDL2 Tx ignores the demodulated B2 data, presenting in its stead the “idle
1s” condition in the IDL2 Rx B2 timeslot (hence, the term “non–transparent”). This bit is reset to 0
by either a software reset, a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(3) — IDL2 B1 Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B1 timeslot
at Din and transmits it onto the Dout pin during the B1 timeslot. Data entering the Din pin during the
B1 timeslot is also transmitted onto the S/T–interface. This bit is reset to 0 by either a software reset,
a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(2) — IDL2 B1 Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B1 channel
timeslot at Din and transmits it onto the Dout pin during the B1 timeslot. Data entering the Din pin during
the B1 timeslot is not transmitted onto the S/T–interface. Instead, the MC145574 transmits idle 1s
onto the B1 channel bits of the S/T–interface. This bit is reset to 0 by either a software reset, a hardware
reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(1) — IDL2 B2 Loopback Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B2 channel
timeslot at Din and transmits it onto the Dout pin during the B2 timeslot. Data entering the Din pin during
the B2 timeslot is also transmitted onto the S/T–interface. This bit is reset to 0 by either a software
reset, a hardware reset, or in the “return to normal” mode (NR0(0) = 1).
BR6(0) — IDL2 B2 Loopback Non–Transparent
This bit is a read/write bit and is applicable to both NT and TE modes of operation when the MC145574
is configured for GCI or IDL2 type interfaces. When this bit is a 0, the MC145574 operates normally.
When this bit is a 1, the MC145574 internally loops back the data received during the B2 channel
timeslot at Din and transmits it onto the Dout pin during the B2 timeslot. Data entering the Din pin during
the B2 timeslot is not transmitted onto the S/T–interface. Instead, the MC145574 transmits idle 1s
onto the B2 channel bits of the S/T–interface. This bit is reset to 0 by either a software reset, a hardware
reset, or in the “return to normal” mode (NR0(0) = 1).
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR7
Activation
Procedures
Disabled
NT: Active
Only NT
Enable
TE: D
Channel
Procedures
Ignored
NT: Enable
Multi–
framing
TE: Not
Applicable
NT: Invert E
Channel
TE: Map E
To IDL2
NT: IDL2
Master
Mode
TE: IDL2
Free Run
IDL2 Clock
Speed
(LSB)
LAPD
Polarity
Control
NT:
Activation
Timer #2
Expired
TE: Not
Applicable
BR7(7) — Activation Procedures Disabled
This bit a read/write bit and is applicable to both NT and TE modes of operation. When this bit is
0, the MC145574 functions normally. When this bit is set to 1, the transmit section of the transceiver
is forced into the highest information state. Thus, if the device is operating as NT, INFO 4 is forced
out on the transmit side of the device. INFO 4 is forced out regardless of what is being received on
RxP/RxN. If the device is operating as a TE, the transceiver transmits INFO 3 on TxP/TxN.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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