參數資料
型號: MC145574
廠商: Motorola, Inc.
英文描述: ISDN S/T-Interface Transceiver
中文描述: 綜合業(yè)務數字網S / T的接口收發(fā)器
文件頁數: 51/164頁
文件大小: 1072K
代理商: MC145574
MC145574
6–5
MOTOROLA
S(2:0), OR5(b2, b1, b0)
These three bits select the GCI timeslot that the device will use. S(2:0)=0 is the default state, timeslot 0.
The timeslot selected must be compatible with the DCL clock rate being used (i.e., if the clock rate
is 2048 kHz, only the first four timeslots are available).
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OR5(b2)
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0
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OR5(b1)
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0
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OR5(b0)
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0
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Timeslot
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
FSC
This is an input/output pin to which all serial interface events are synchronized. This pin is periodic
at 8 kHz/125
μ
s. In the master mode, the pin is an output and is either derived from the S/T frame
or from XTAL. In the slave mode, the pin is an input.
DCL
This is an input/output pin that provides the clock to the serial interface. In the master mode, this pin
is an output; and in the slave mode, it is an input. The clock is continuous and is synchronous with
the frame sync. The clock rate for GCI is double the bit rate (i.e., two clocks per data bit).
When programmed as an input, the clock rate can be any multiple of 16 kHz between 512 and
4096 kHz.
When programmed as an output, the clock rate can be selected via the SCP GCI control register
to be either 2048, 1536, or 512 kHz.
Din
This pin is always an input. Data to be output on the S/T–interface is input on this pin during the pro-
grammed timeslots. This pin is also the input for the monitor and C/I channels of the GCI frame.
Dout
This pin is an open drain output and requires an external pull–up resistor. This output can be wire–OR’d
with other GCI devices. Data received on the S/T–interface is output on this pin during the programmed
timeslot and is high impedance at all other times. This pin is also the output for the monitor and C/I
channels of the GCI frame.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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