參數(shù)資料
型號： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù)： 34/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
4–8
MOTOROLA
NT
NT
NT
NT
TE
TE
TE
TE
CLK
SYNC
DATA
CLK
SYNC
DATA
CLK
SYNC
DATA
CLK
SYNC
DATA
CLK
CLK
SYNC
DATA
TFSC
CLK
SYNC
DATA
TFSC
CLK
SYNC
DATA
TFSC
CLK
SYNC
DATA
TFSC
S
S
S
S
T
T
T
T
FRAME SYNC
CONTROL
BUS
SUBSCRIBER
LINES
S–INTERFACE
TRUNK LINES
TO CENTRAL OFFICE(S)
T–INTERFACE
FSC SOURCE
SELECTOR
SYNC AND CLOCK
GENERATOR
TSA CONTROLLER
Figure 4–4. Example Architecture of an NT2
Independent timeslot assignment is available for the B1, B2, and D channels in both the transmit and
receive directions. B1, B2, and D timeslots may be enabled separately. When a timeslot is enabled,
the IDL2 automatically enters timeslot mode. If any one channel’s timeslot is not enabled, data trans-
mitted by the framer for that channel will be filled with all ones, and the channel will not be present
on Dout.
With a DCL rate of 4096 kHz, it is possible to allocate 1 of 256 possible timeslots to each data channel.
It is important that the software selects a timeslot consistent with the DCL rate. When a clock rate
of 2048 kHz is being used, only 128 timeslots are available. If a timeslot out with the available range
is chosen, then no data transfer occurs for that timeslot.
The default values assigned to the B1, B2, and D channels are 00H, 04H, and 08H. These values
provide an IDL2 8–bit output format as default.
The IDL2 10–bit mode is not available when the timeslot assigner has been enabled.
CAUTION
Do not program overlapping timeslots even if a timeslot has not been enabled. The transmit
and receive timeslot for a given B1, B2, or D channel can be the same.
In master timing mode, the default state is to supply a one–clock–wide FSC/FSR/FST frame sync.
However, an option is provided to change this to long frame. The length of the long frame pulse is
always 8–bit clocks, regardless of whether an 8– or 10–bit format is selected. In the slave mode, the
MC145574 will automatically adjust to whichever framing method is supplied. If the frame sync is two
or more clocks wide, the MC145574 assumes a long frame format.
A long frame format cannot be used in timeslot assignment mode.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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相關(guān)PDF資料
PDF描述
MC14559BDWR2 Successive Approximation Registers
MC14559B Successive Approximation Registers
MC14559BCP Successive Approximation Registers
MC1455 Timing Circuit
MC1455BD Timing Circuit
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MC145574ADW 功能描述:IC TRANSCEIVER ISDN 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
MC145574ADWR2 功能描述:IC TRANSCEIVER ISDN 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
MC145574AEG 制造商:Freescale Semiconductor 功能描述:
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