- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382298 > MC145574 (Motorola, Inc.) ISDN S/T-Interface Transceiver PDF資料下載
參數(shù)資料
| 型號： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁數(shù)： | 79/164頁 |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁當(dāng)前第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁
MC145574
9–3
MOTOROLA
The functions that were related to the IDL2 M FIFO of the MC145474 have been removed; writing
to this register has no effect, and reading it returns FFH. (No register shown.)
The functions that were related to the IDL2 A FIFO of the MC145474 have been removed; writing
to this register has no effect, and reading it returns FFH. (No register shown.)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR2
NT: SC1.1
TE: Q.1
NT: SC1.2
TE: Q.2
NT: SC1.3
TE: Q.3
NT: SC1.4
TE: Q.4
BR2(7:4)
NT: Subchannel 1 (SC1) to S/T Loop
— BR2(7:4) are used for multiframing. In the NT mode of opera-
tion, these four bits correspond to subchannel 1 for transmission to the TE(s). Multiframing is initiated
by the NT by setting BR7(5). When multiframing is enabled, the NT will transmit the bits in BR2(7:4)
as subchannel 1, in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605. BR2(7:4),
is internally polled at the start of every multiframe (this occurs every 5 ms and the device can be pro-
grammed to give an interrupt at the start of every multiframe), and its contents are interpreted as
subchannel 1. If multiframing is enabled and the contents of BR2(7:4) have not been updated, then
the subchannel is re–transmitted as is. BR2(7:4) can be updated any time between the 5 ms interrupts.
BR2(7:4) are read/write bits. Application of either a software or hardware reset resets these bits to
all 0s. Note that BR2(7) is the MSB of SC1 and BR2(4) is the LSB. Refer to Section 10 for a more
detailed description of this feature.
TE: Q Nibble to S/T Loop
— BR2(7:4) are used for multiframing. In the TE mode of operation these
four bits correspond to the Q channel data for transmission to the NT. When multiframing is enabled,
the TE will transmit the bits in BR2(7:4), as Q channel data, in accordance with CCITT I.430, ETSI
ETS 300012, and ANSI T1.605. BR2(7:4) is internally polled at the start of every multiframe (this occurs
every 5 ms and the device can be programmed to give an interrupt at the start of every multiframe),
and its contents are interpreted as Q channel data. If multiframing is enabled and the contents of
BR2(7:4) have not been updated then the Q channel is re–transmitted as is. BR2(7:4) can be updated
any time between the 5 ms interrupts. BR2(7:4) are read/write bits. Application of either a software
or hardware reset sets these bits to all 1s. Note that BR2(7) is the MSB of the Q channel and BR2(4)
is the LSB. Refer to Section 10 for a more detailed description of this feature.
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR3
NT: Q.1
TE: SC1.1
NT: Q.2
TE: SC1.2
NT: Q.3
TE: SC1.3
NT: Q.4
TE: SC1.4
NT: Q Qual
TE: Not
Applicable
Interrupt
Every
Multiframe
BR3(7:4)
NT: Q Nibble from S/T Loop
— BR3(7:4) are used in the multiframing mode of operation. When
the device is configured as an NT and multiframing has been enabled, these bits correspond to the
received Q channel nibble from the TE(s). These bits are updated once every multiframe. The NT–con-
figured device can give an interrupt once every multiframe (see BR3(2) and NR4(2)) or every time
a new Q channel nibble is received. BR3(7:4) are read only bits. Application of either a hardware
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC14559BDWR2 | Successive Approximation Registers |
| MC14559B | Successive Approximation Registers |
| MC14559BCP | Successive Approximation Registers |
| MC1455 | Timing Circuit |
| MC1455BD | Timing Circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC145574AAC | 功能描述:IC TRANSCEIVER ISDN 32-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145574AACR2 | 功能描述:IC TRANSCEIVER ISDN 32-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145574ADW | 功能描述:IC TRANSCEIVER ISDN 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145574ADWR2 | 功能描述:IC TRANSCEIVER ISDN 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| MC145574AEG | 制造商:Freescale Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。