參數(shù)資料
型號： MC145574
廠商： Motorola, Inc.
英文描述： ISDN S/T-Interface Transceiver
中文描述： 綜合業(yè)務數(shù)字網S / T的接口收發(fā)器
文件頁數(shù)： 74/164頁
文件大?。?/td> 1072K
代理商： MC145574
MC145574
8–6
MOTOROLA
NR4(3) — Enable IRQ3
NR4(3) is an interrupt mask bit for IRQ3. When this bit is set high and IRQ3 is pending (i.e., NR3(3)
having been internally set to a 1), an interrupt is given to an external device by holding the IRQ* pin
low. The IRQ* pin will be held low until the interrupt condition is cleared by writing a 0 to NR3(3).
When the interrupt mask bit NR4(3) is a 0, NR3(3) cannot cause an interrupt to the external device.
This bit can be reset by either a software or hardware reset. Note that NR4(3) is a read/write bit.
NR4(2) — Enable IRQ2
NR4(2) is an interrupt mask bit for IRQ2. When this bit is set high and IRQ2 is pending (i.e., NR3(2)
having been internally set to a 1), an interrupt is given to an external device by holding the IRQ* pin
low. The IRQ* pin will be held low until the interrupt condition is cleared by reading BR3. When the
interrupt mask bit (NR4(2)) is a 0, NR3(2) cannot cause an interrupt to the external device. This bit
can be reset by either a software or a hardware reset. Note that NR4(2) is a read/write bit.
NR4(1) — NT: Enable IRQ6
TE: Enable IRQ1
NR4(1) is an interrupt mask bit for IRQ1 or IRQ6. When this bit is set high and IRQ1 is pending (i.e.,
NR3(1) having been internally set to a 1), an interrupt is given to an external device by holding the
IRQ* pin low. The IRQ* pin will be held low until the interrupt condition is cleared by writing a 0 to
NR3(1). When the interrupt mask bit NR4(1) is a 0, NR3(1) cannot cause an interrupt to the external
device. This bit can be reset by either a software or a hardware reset. Note that NR4(1) is a read/write
bit.
NR4(0) — NT: Enable IRQ7
TE: Not Applicable
NR4(0) is an interrupt mask bit for IRQ7. When this bit is set high and IRQ7 is pending (i.e., NR3(0)
having been internally set to a 1), an interrupt is given to an external device by holding the IRQ* pin
low. The IRQ* pin will be held low until the interrupt condition is cleared by writing a 0 to NR3(0).
When the interrupt mask bit NR4(0) is a 0, NR3(0) cannot cause an interrupt to the external device.
This bit can be reset by either a software or a hardware reset. Note that NR4(0) is a read/write bit.
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 5 (NR5) follows.
b3
b2
b1
b0
NR5
NT: Idle B1 Channel
TE: Enable B1 Channel
NT: Idle B2 Channel
TE: Enable B2 Channel
Invert B1 Channel
Invert B2 Channel
rw
rw
rw
rw
NR5(3)
NT: Idle B1 Channel
— In the NT mode, NR5(3) functions as a B1 channel idle bit. When NR5(3)
is 0, the MC145574 functions normally where data received in the B1 channel timeslot via the IDL2
is modulated onto the S/T–interface in the B1 channel timeslot. When NR5(3) is 1, data input on the
IDL2 Rx pin in the B1 channel timeslot is ignored, and the “idle 1s” condition exists on the B1 channel
timeslot on the S/T–interface. Note that the default condition (i.e., after power–up or after a reset)
for NR5(3) is 0, thereby allowing the data received via the IDL2 interface to be modulated onto the
transmission loop. Note that NR5(3) is a read/write bit in the NT mode.
TE: Enable B1 Channel
— In the TE mode of operation, NR5(3) functions as a B1 channel enable
bit. In the TE mode B1 channel data is forced to the “idle 1s” condition on the S/T transmission loop
when NR5(3) is 0. When NR5(3) is 1 (enabled), B1 channel data input via the IDL2 interface is modu-
lated and transmitted onto the S/T transmission loop in the B1 channel timeslot. The default condition
(i.e., after power–up or after a reset) for TE mode devices forces the B1 channel bits to the “idle 1s”
condition. This is to avoid B channel interference until the B channels are assigned by the network.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC145574AEG 制造商:Freescale Semiconductor 功能描述:
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