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參數(shù)資料
| 型號(hào)： | MC145574 |
| 廠商： | Motorola, Inc. |
| 英文描述： | ISDN S/T-Interface Transceiver |
| 中文描述： | 綜合業(yè)務(wù)數(shù)字網(wǎng)S / T的接口收發(fā)器 |
| 文件頁(yè)數(shù)： | 84/164頁(yè) |
| 文件大?。?/td> | 1072K |
| 代理商： | MC145574 |
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MC145574
9–8
MOTOROLA
signals will be free–running (derived from the crystal). If the loop is active, these signals will be synchro-
nous to the inbound data. This bit is a read/write bit and is reset to 0 by application of either a software
or a hardware reset.
BR7(2) — IDL2 Clock Speed (LSB)
This bit is a read/write bit and is applicable to both NT and TE modes of operation. BR7(2), in conjunc-
tion with BR13(5), determines the IDL2 CLK frequency when operating in the IDL2 master mode.
BR7(2) is the LSB and BR13(5) is the MSB. The code corresponding to each IDL2 clock frequency
is shown in Table 9–4.
Table 9–4. IDL2 Clock Speed Codes
IDL2 CLK
BR13(5)
BR7(2)
Rate
Duty Cycle
0
0
2.56 MHz
50%
0
1
2.048 MHz
53.3%
1
0
1.536 MHz
50%
1
1
512 kHz
50%
Application of either a hardware or a software reset will reset this bit to 0. Refer to Section 4 for a
more detailed description of this feature.
BR7(1) — NT: LAPD Polarity Control (NT Terminal Mode)
TE: LAPD Polarity Control
When the MC145574 is configured as a TE or an NT (Terminal Mode), this bit performs the “LAPD
Polarity Control” function. When this bit is 0, the active state of DREQUEST and DGRANT signals
is defined to be the logic 1 or high state. When this bit is 1, the active state of these signals is defined
to be the logic 0 or low state. This bit is a read/write bit and is reset to 0 by application of either a
hardware or software reset.
BR7(0) — NT: Activation Timer #2 Expired
TE: Not Applicable
When the MC145574 is configured as an NT, this bit performs the “Activation Timer #2 Expired” func-
tion. When this bit is 0, the NT–configured S/T transceiver uses a value of 50 ms for the Timer #2
value outlined in CCITT I.430, ETSI ETS 300012, and ANSI T1.605 (i.e., the device unambiguously
detects INFO 1). When this bit is 1, a value of 100 ms is used for the value of Timer #2. This bit is
a read/write bit and is reset to 0 by application of either a hardware or software reset.
The functions that were related to the IDL2 A/M FIFOs have been removed. Writing to these registers
will have no effect, and reading them will return 00H or any value that has been written to them. (No
register shown.)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
BR9
NT:
TXSC2.1
TE:
RXSC2.1
NT:
TXSC2.2
TE:
RXSC2.2
NT:
TXSC2.3
TE:
RXSC2.3
NT:
TXSC2.4
TE:
RXSC2.4
NT:
TXSC3.1
TE:
RXSC3.1
NT:
TXSC3.2
TE:
RXSC3.2
NT:
TXSC3.3
TE:
RXSC3.3
NT:
TXSC3.4
TE:
RXSC3.4
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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