參數(shù)資料
型號: MC145574
廠商: Motorola, Inc.
英文描述: ISDN S/T-Interface Transceiver
中文描述: 綜合業(yè)務數(shù)字網(wǎng)S / T的接口收發(fā)器
文件頁數(shù): 91/164頁
文件大?。?/td> 1072K
代理商: MC145574
MC145574
10–1
MOTOROLA
There are eleven overlay registers (OR0 through OR9 and OR15) in the MC145574. The overlay regis-
ters are a second bank of registers available when the overlay register control bit BR15(7) is set to
a logic 1. These overlay registers are in the IDL2 TSA mode used to assign the timeslot used by each
channel (B1, B2, and D) for transmission and reception; OR0 through OR5, OR6, OR7, and OR8
are control registers used in the GCI indirect mode, and OR15 gives the revision number of the S/T
chip.
Table 10–1. Overlay Register Map
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
OR0
Din B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
Din B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
Din D Channel Timeslot Bits (7:0) (IDL2 Mode)
Dout B1 Channel Timeslot Bits (7:0) (IDL2 Mode)
Dout B2 Channel Timeslot Bits (7:0) (IDL2 Mode)
Dout D Channel Timeslot Bits (7:0) (IDL2 Mode)
Time Slot Assignment for GCI Mode
OR1
OR2
OR3
OR4
OR5
OR5
S2
S1
S0
OR6
TSA B1
Enable
TSA B2
Enable
TSA D
Enable
Dout Open
Drain
GCI Indirect
Mode Enable
CLK1
CLK0
OR7
Disable
3 V
Regulator
Enable
S/G Bit
Enable
TCLK
Dual Frame
Syncs
Long
Frame
8/10 Bit
Select
TSEN B1/B2
Enable,
BCL Enable
TSEN
D Channel
Enable
OR8
Reserved
Disable XTAL
TE Mode
Enable
Master Mode
Enable
FIX Enable
NT Terminal
Mode Enable
Sleep
Enable
OR9
Force
INFO 2
Transmission
T3F8
Enable
T3F6
Disable
OR15
Overlay
Register
Enable
Rev 5
Rev 4
Rev 3
Rev 2
Rev 1
Rev 0
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料
PDF描述
MC14559BDWR2 Successive Approximation Registers
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MC14559BCP Successive Approximation Registers
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